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product specification high performance 8-bit microcontrollers z8 encore! xp ? f0822 series ps022517-0508 copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com product specification
ps022517-0508 z8 encore! xp ? f0822 series product specification do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crim zon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
ps022517-0508 revision history z8 encore! xp ? f0822 series product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page number may 2008 17 removed flash microcontrollers from the title throughout the document. all february 2008 16 updated the flag status for bclr, bit, and bset in table 126. 219 december 2007 15 updated zilog logo, zilog text, disclaimer section, and implemented style guide. updated z8 encore! 8k series to z8 encore ! xp f0822 series flash microcontrollers throughout the document. all june 2007 and august 2007 13 and 14 no changes. all december 2006 12 updated ordering information and minor edits done. all
ps022517-0508 table of contents z8 encore! xp ? f0822 series product specification iv table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x about this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x intended audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x manual conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii abbreviations/acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ez8 cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 information area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ps022517-0508 table of contents z8 encore! xp ? f0822 series product specification v reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 voltage brownout reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 watchdog timer reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 stop mode recovery using wdt time-out . . . . . . . . . . . . . . . . . . . . . . . . 44 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . 44 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 port a?c address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 port a?c control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 port a?c output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 63 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 64 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ps022517-0508 table of contents z8 encore! xp ? f0822 series product specification vi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 timer output signal operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . 79 timer 0?1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 79 timer 0?3 control 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 timer 0?1 control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 watchdog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . . 85 watchdog timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 86 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 watchdog timer reload upper, high and low byte registers . . . . . . . . . . 87 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 89 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 transmitting data using polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 transmitting data using interrupt-driven method . . . . . . . . . . . . . . . . . . . . 92 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 receiving data using interrupt-driven method . . . . . . . . . . . . . . . . . . . . . . 94 clear to send operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 uart control register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 uart receive data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . 103 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . 106 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ps022517-0508 table of contents z8 encore! xp ? f0822 series product specification vii operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 infrared endec control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 spi clock phase and polarity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 multi-master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 spi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 spi control register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 spi mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 spi diagnostic state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 spi baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 125 i2c controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 sda and scl signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 i 2 c interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 software control of i2c transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 master write and read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 address only transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . 131 write transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 address only transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . 133 write transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . 134 read transaction with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 read transaction with a 10-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . 137 i2c control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 i2c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 i2c status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 i2c control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 i2c baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 143 i2c diagnostic state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ps022517-0508 table of contents z8 encore! xp ? f0822 series product specification viii i2c diagnostic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 automatic power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 adc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 information area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 timing using the flash frequenc y registers . . . . . . . . . . . . . . . . . . . . . . 155 flash read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 page erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . 159 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . . 161 option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 flash memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 flash memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 oscillator operation with an exte rnal rc network. . . . . . . . . . . . . . . . . . . . . . 168 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ps022517-0508 table of contents z8 encore! xp ? f0822 series product specification ix ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 ocdcntr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . 181 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . . 195 general purpose i/o port input data sample timing . . . . . . . . . . . . . . . . 200 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . 201 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . 209 assembly language syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ez8 cpu instruction notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 condition codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ez8 cpu instruction summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification x introduction this product specification provides detailed operating in formation for z8 encore! xp ? f0822 series devices within the z8 encore ! xp microcontroller (mcu) family of prod- ucts. within this document, z8 encore! xp ? f0822 series is referre d as z8 encore! xp or the f0822 series unless specifically stated otherwise. about this manual zilog recommends that you read and understand everything in this ma nual before setting up and using the product. we have designed this product specification to be used either as a how to procedural manual or a reference guide to important data. intended audience this document is written for zilog customer s who are experienced at working with micro- controllers, integrated circuits , or printed circuit assemblies. manual conventions the following assumptions and conventions are adopted to provide clarity and ease of use: courier typeface commands, code lines and fragments, bits, eq uations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the courier typeface. where the use of the font is not indicated, as in the index, the name of the entity is pre- sented in upper case. ? example : flags[1] is smrf . hexadecimal values hexadecimal values are de signated by uppercase h suffix and appear in the courier typeface. ? example : r1 is set to f8h. brackets the square brackets [ ], indicate a register or bus. ? example : for the register r1[7:0], r1 is an 8-bit register, r1[7] is the most significant bit, and r1[0] is the least significant bit.
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification xi braces the curly braces { }, indicate a single register or bus created by concatenating some com- bination of smaller registers, buses, or individual bits. ? example : the 12-bit register address { 0h , rp[7:4], r1[3:0]} is composed of a 4-bit hexadecimal value ( 0h ) and two 4-bit register values taken from the register pointer (rp) and working register r1. 0h is the most significant ni bble (4-bit value) of the 12-bit register, and r1[3:0] is the least significant nibble of the 12-bit register. parentheses the parentheses ( ), indicate an indirect register address lookup. ? example : (r1) is the memory location refere nced by the address contained in the working register r1. parentheses/bracket combinations the parentheses ( ), indicate an indirect regi ster address lookup and the square brackets, [ ], indicate a register or bus. ? example : assume pc[15:0] contains the value 1234h . (pc [15:0]) then refers to the contents of the memory location at address 1234h . use of the words set , reset and clear the word set implies that a register bit or a cond ition contains a logical 1. the words re set or clear imply that a register bit or a condition co ntains a logical 0. when either of these terms is followed by a number, the word logical cannot be included; however, it is implied. notation for bits and similar registers a field of bits within a register is designated as: register[ n : n ]. ? example : addr[15:0] refers to bits 15 through bit 0 of the address. use of the terms lsb , msb , lsb , and msb in this document, the terms lsb and msb, when appearing in upper case, mean least significant byte and most significant byte , respectively. the lowercase forms, lsb and msb , mean least significant bit and most significant bit , respectively. use of initial uppercase letters initial uppercase letters designate settin gs and conditions in general text. ? example 1 : the receiver forces the scl line to low. ? example 2 : the master generates a stop condition to abort the transfer.
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification xii use of all uppercase letters the use of all uppercase letters designates the names of states, modes, and commands. ? example 1 : the bus is considered busy after the start condition. ? example 2 : a start command triggers the processing of the initialization sequence. ? example 3 : stop mode. bit numbering bits are numbered from 0 to n?1 where n indicates the total number of bits. for example, the 8 bits of a register are numbered from 0 to 7. safeguards it is important that you unde rstand the following safety te rms, which are defined here. indicates a procedure or file can be come corrupted if you does not follow directions. abbreviations/acronyms this document uses the following abbreviations or acronyms. abbreviations/ acronyms expansion adc analog-to-digital converter lpo low-power operational amplifier spi serial peripheral interface wdt watchdog timer gpio general-purpose input/output ocd on-chip debugger por power-on reset lvd low-voltage detection vbo voltage brownout isr interrupt service routine uart universal asynchronou s receiver/transmitter irda infrared data association i 2 c inter-integrated circuit caution:
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification xiii pdip plastic dual inline package soic small outline integrated circuit ssop small shrink outline package pc program counter irq interrupt request abbreviations/ acronyms expansion
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification 1 introduction zilog?s z8 encore! xp ? mcu product family is a line of zilog microcontrollers based on the 8-bit ez8 cpu. z8 encore! xp ? f0822 series, hereafter re ferred as z8 encore! xp or the 8k series adds flash memory to zilog?s extensive line of 8-bit microcontrollers. the flash in-circuit programming allows faster de velopment time and program changes in the field. the new ez8 cpu is upward -compatible with the existing z8 ? instructions. the rich peripheral set of z8 encore! xp makes it suitable for a variety of applications includ- ing motor control, security systems, home appliances, personal electronic devices, and sensors. features the features of z8 encore! xp mcu product family include: ? 20 mhz ez8 cpu core ? up to 8 kb flash with in-c ircuit programming capability ? 1 kb register ram ? optional 2- to 5-channel, 10-bit analog-to-digital converter (adc) ? full-duplex 9-bit universal asynchronous receiver/transmitter (uart) with bus transceiver driver enable control ? inter-integrated circuit (i 2 c) ? serial peripheral interface (spi) ? infrared data association (irda)-com pliant infrared encoder/decoders ? two 16-bit timers with capture, compare, and pwm capability ? watchdog timer (wdt) with internal rc oscillator ? 11 to 19 input/output pins depending upon package ? up to 19 interrupts with configurable priority ? on-chip debugger (ocd) ? voltage brownout (vbo) protection ? power-on reset (por) ? crystal oscillator with three po wer settings and rc oscillator option
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification 2 ? 2.7 v to 3.6 v operating voltage with 5 v-tolerant inputs ? 20-pin and 28-pin packages ? 0 c to +70 c standard temperature and -40 c to +105 c extended temperature operating ranges part selection guide table 1 identifies the basic features and package styles available for each device within the z8 encore! xp ? f0822 series product line. table 1. z8 encore! xp ? f0822 series part selection guide part number flash (kb) ram (kb) i/o 16-bit timers with pwm adc inputs uarts with irda i 2 cspi package pin counts 20 28 z8f0822 8 1 19 2 5 1 1 1 x z8f0821 8 1 11 2 2 1 1 x z8f0812 8 1 19 2 0 1 1 1 x z8f0811 8 1 11 2 0 1 1 x z8f0422 4 1 19 2 5 1 1 1 x z8f0421 4 1 11 2 2 1 1 x z8f0412 4 1 19 2 0 1 1 1 x z8f0411 4 1 11 2 0 1 1 x
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification 3 block diagram figure 1 displays the block diagram of the architecture of z8 encore! xp ? f0822 series devices . figure 1. z8 encore! xp ? f0822 series block diagram cpu and peripheral overview ez8 cpu features zilog?s latest ez8 8-bit cpu, meets the contin uing demand for faster and more code-effi- cient microcontrollers. the ez8 cpu exec utes a superset of the original z8 ? instruction set. gpio irda uart i 2 c timers spi adc flash flash controller ram ram controller memory interrupt controller on-chip debugger ez8 cpu wdt with rc oscillator por/vbo & reset controller crystal oscillator register bus memory buses system clock
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification 4 the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and d ecreasing the required program memory. ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks. ? compatible with existing z8 ? code. ? expanded internal register file allows access of up to 4 kb. ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c. ? pipelined instruction fetch and execution. ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl. ? new instructions support 12-bit linear addressing of the register file. ? up to 10 mips operation. ? c-compiler friendly. ? 2 to 9 clock cycles per instruction. for more information regard ing the ez8 cpu, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . general purpose input/output z8 encore! xp ? f0822 series features 11 to 19 port pins (ports a?c) for general purpose input/output (gpio). the number of gpio pins available is a function of package. each pin is individually programmable. ports a and c supports 5 v-tolerant inputs. flash controller the flash controller programs and erases the flash memory. 10-bit analog-to-digital converter the optional analog-to-digital converter (adc ) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from 2 to 5 different analog input sources. uart the universal asynchronous r eceiver/transmitter (uart) is full-duplex and capable of handling asynchronous data transfers. the uar t supports 8-bit and 9-bit data modes and selectable parity.
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification 5 i 2 c the inter-integrated circuit (i 2 c) controller makes the z8 enco re! xp compatible with the i 2 c protocol. the i 2 c controller consists of two bidi rectional bus lines, a serial data (sda) line, and a serial clock (scl) line. serial peripheral interface the serial peripheral interface (spi) allows th e z8 encore! xp to exchange data between other peripheral devices such as eeproms, a/d converters, and isdn devices. the spi is a full-duplex, synchronous, and character-oriented channel that supports a four-wire interface. timers two 16-bit reloadable timers are used for tim ing/counting events or for motor control operations. these timers provide a 16-bit prog rammable reload counter and operate in one-shot, continuous, gated, capture, compare, capture and compare, and pwm modes. interrupt controller z8 encore! xp ? f0822 series products support up to 18 interrupts. these interrupts con- sist of 7 internal peripheral interrupts and 11 gpio pin interrupt sources. the interrupts have 3 levels of programm able interrupt priority. reset controller z8 encore! xp f0822 series products are reset using the reset pin, por, wdt, stop mode exit, or vbo warning signal. on-chip debugger z8 encore! xp f0822 series products featur e an integrated on-chip debugger (ocd). the ocd provides a rich-set of debugging capa bilities, such as, reading and writing regis- ters, programming the flash, setting breakpoints, and executing code. a single-pin inter- face provides communi cation to the ocd.
ps022517-0508 introduction z8 encore! xp ? f0822 series product specification 6
ps022517-0508 signal and pin descriptions z8 encore! xp ? f0822 series product specification 7 signal and pin descriptions z8 encore! xp ? f0822 series products are available in a variety of packages, styles, and pin configurations. this chapter describes the signals and available pin configurations for each of the package styles. for information re garding the physical p ackage specifications, see packaging on page 233. available packages table 2 identifies the package styles available for each device with in z8 encore! xp f0822 series product line. pin configurations figure 2 through figure 5 display the pin configurations for all of the packages available in z8 encore! xp f0822 series. see table 4 for a description of the signals. the analog input alternate functions (anax) are not available on z8 encore! xp ? f0822 series devices. table 2. z8 encore! xp f0822 series package options part number 10-bit adc 20-pin ssop and pdip 28-pin soic and pdip z8f0822 yes x z8f0821 yes x z8f0812 no x z8f0811 no x z8f0422 yes x z8f0421 yes x z8f0412 no x z8f0411 no x note:
ps022517-0508 signal and pin descriptions z8 encore! xp ? f0822 series product specification 8 figure 2. z8f0821 and z8f0421 in 20-pin ssop and pdip packages figure 3. z8f0822 and z8f0422 in 28-pin soic and pdip packages figure 4. z8f0811 and z8f0411 in 20-pin ssop and pdip packages pc0 / t1in pb0 / ana0 pb1 / ana1 vref av ss av dd dbg pa5 / txd0 pa4 / rxd0 pa6 / scl pa7 / sda reset v ss xin xout v dd pa0 / t0in 1 pa3 / cts0 pa1 / t0out 5 10 pa2 / de0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb0 / ana0 pb1 / ana1 pb2 / ana2 pb3 / ana3 pb4 / ana4 vref av ss av dd dbg pc0 / t1in pa6 / scl pa7 / sda reset v ss xin xout v dd 1 pc1 / t1out pc5 / miso 5 10 pc4 / mosi pc3 / sck pc2 / ss pa0 / t0in 14 pa1 / t0out 2 3 4 6 7 8 9 11 12 13 pa5 / txd0 pa4 / rxd0 pa3 / cts0 pa2 / de0 28 24 19 15 27 26 25 23 22 21 20 18 17 16 pc0 / t1in pb0 pb1 no connect av ss av dd dbg pa5 / txd0 pa4 / rxd0 pa6 / scl pa7 / sda reset v ss xin xout v dd pa0 / t0in 1 pa3 / cts0 pa1 / t0out 5 10 pa2 / de0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12
ps022517-0508 signal and pin descriptions z8 encore! xp ? f0822 series product specification 9 figure 5. z8f0812 and z8f0412 in 28-pin soic and pdip packages signal descriptions table 3 describes z8 encore! xp ? f0822 series signals. see pin configurations on page 7 to determine the signals availabl e for the specific package styles . table 3. signal descriptions signal mnemonic i/o description general-purpose i/o ports a-h pa[7:0] i/o port c ?these pins are used for general-purpose i/o and supports 5 v-tolerant inputs. pb[4:0] i/o port b ?these pins are used for general-purpose i/o. pc[5:0] i/o port c ?these pins are used for general-purpose i/o and support 5 v-tolerant inputs. i 2 c controller scl i/o serial clock ?this open-drain pin clocks data transfers in accordance with the i 2 c standard protocol. this pin is multip lexed with a gpio pin. when the gpio pin is configured for alternate function to enable the scl function, this pin is open-drain. sda i/o serial data ?this open-drain pin transfers data between the i 2 c and a slave. this pin is multiplexed with a gpio pin. when the gpio pin is configured for alternate function to enable the sda function, this pin is open-drain. pb0 pb1 pb2 pb3 pb4 no connect av ss av dd dbg pc0 / t1in pa6 / scl pa7 / sda reset v ss xin xout v dd 1 pc1 / t1out pc5 / miso 5 10 pc4 / mosi pc3 / sck pc2 / ss pa0 / t0in 14 pa1 / t0out 2 3 4 6 7 8 9 11 12 13 pa5 / txd0 pa4 / rxd0 pa3 / cts0 pa2 / de0 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps022517-0508 signal and pin descriptions z8 encore! xp ? f0822 series product specification 10 spi controller ss i/o slave select ?this signal can be an output or an input. if the z8 encore! xp ? is the spi master, this pin can be confi gured as the slave select output. if the z8 encore! xp is the spi slave, this pin is the input slave select. it is multiplexed with a gpio pin. sck i/o spi serial clock ?the spi master supplies this pin. if the z8 encore! xp is the spi master, this pin is the output. if the z8 encore! xp is the spi slave, this pin is the input. it is multiplexed with a gpio pin. mosi i/o master-out/slave-in ?this signal is the data output from the spi master device and the data input to the spi slav e device. it is multiplexed with a gpio pin. miso i/o master-in/slave-out ?this pin is the data input to the spi master device and the data output from the spi slave de vice. it is multiplexed with a gpio pin. uart controllers txd0 o transmit data ?this signal is the transmit output from the uart and irda. the txd signals are multip lexed with gpio pins. rxd0 i receive data ?this signal is the receiver input for the uart and irda. the rxd signals are multiplexed with gpio pins. cts0 i clear to send ?this signal is control inputs for the uart. the cts signals are multiplexed with gpio pins. de0 o driver enable ?this signal allows automatic control of external rs-485 drivers. this signal is approximately the inverse of the txe (transmit empty) bit in the uart status 0 register. the de signal can be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out / t1out o timer output 0?1 ?these signals are output pins from the timers. the timer output signals are multiplexed with gpio pins. t0in / t1in i timer input 0?1 ?these signals are used as th e capture, gating and counter inputs. the timer input signals ar e multiplexed with gpio pins. analog ana[4:0] i analog input ?these signals are inputs to the analog-to-digital converter (adc). the adc analog inputs ar e multiplexed with gpio pins. vref i analog-to-digital converter reference voltage input ?as an output, the vref signal is not recommended for us e as a reference voltage for external devices. if the adc is configured to use the internal reference voltage generator, this pin should be left unconnected or capacitively coupled to analog ground (avss). table 3. signal descriptions (continued) signal mnemonic i/o description
ps022517-0508 signal and pin descriptions z8 encore! xp ? f0822 series product specification 11 oscillators xin i external crystal input ?this is the input pin to the crystal oscillator. a crystal is connected between the external crystal input and the xout pin to form the oscillator. in addition, this pin is used with external rc networks or external clock drivers to provide the system clock to the system. xout o external crystal output ?this pin is the output of the crystal oscillator. a crystal is connected between external cr ystal output and the xin pin to form the oscillator. when the system clock is re ferred in this manual, it refers to the frequency of the signal at this pin. this pin must be left unconnected when not using a crystal. on-chip debugger dbg i/o debug ?this pin is the control and data input and output to and from the ocd. this pin is open-drain. for operation of the ocd, all power pins (v dd and av dd ) must be supplied with power and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must have an external pull-up resistor to ensure proper operation. reset reset i reset ?generates a reset when asserted (driven low). power supply v dd i digital power supply. av dd i analog power supply ?must be powered up and grounded to vdd, even if not using analog features. v ss i digital ground. av ss i analog ground ?must be grounded and connected to vss, even if not using analog features. table 3. signal descriptions (continued) signal mnemonic i/o description caution:
ps022517-0508 signal and pin descriptions z8 encore! xp ? f0822 series product specification 12 pin characteristics table 4 provides detailed inform ation on the characteristics for each pin available on z8 encore! xp ? f0822 series products. table 4 data is sorted alph abetically by the pin symbol mnemonic. table 4. pin characteristics symbol mnemonic direction reset direction active low or active high tri-state output internal pull-up or pull-down schmitt-trigger input open drain output av dd n/a n/a n/a n/a no no n/a av ss n/a n/a n/a n/a no no n/a dbg i/o i n/a yes no yes yes pa[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pb[4:0] i/o i n/a yes programmable pull-up yes yes, programmable pc[5:0] i/o i n/a yes programmable pull-up yes yes, programmable reset i i low n/a pull-up yes n/a v dd n/a n/a n/a n/a no no n/a vref analog n/a n/a n/a no no n/a v ss n/a n/a n/a n/a no no n/a xin i i n/a n/a no no n/a xout o o n/a no no no no
ps022517-0508 address space z8 encore! xp ? f0822 series product specification 13 address space the ez8 cpu accesses three distinct address spaces: ? the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral, and gpio port control registers. ? the program memory contains addresses for all memory locations having executable code and/or data. ? the data memory contains addresses for all memory locations that hold data only. these three address spaces are covered briefl y in the following secti ons. for more infor- mation on the ez8 cpu and its address space, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . register file the register file address space in the z8 encore! xp ? is 4 kb (4096 bytes). it is com- posed of two sections?control registers and general-purpose registers. when instruc- tions are executed, registers are read from when defined as sources and written to when defined as destinations. the architecture of th e ez8 cpu allows all general-purpose regis- ters to function as accumulators, address pointe rs, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 1 kb register file address space is reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256-byte control register section is reserved (unavailable). reading from the reserved register file addresses returns an undefined value. writing to re served register file addresses is not recom- mended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. z8 encore! xp f0822 series contains 1 kb of on-chip ram. reading from register file addresses outside the available ram addresses (a nd not within the control register address space) returns an undefined va lue. writing to these register file addresses produces no effect. program memory the ez8 cpu supports 64 kb of progra m memory address space. z8 encore! xp ? f0822 series contain 4 kb to 8 kb on-chip flash in the program memory address space, depending on the device. reading from progra m memory addresses outside the available flash addresses returns ffh . writing to unimplemented prog ram memory addresses pro- duces no effect . table 5 describes the program memory ma ps for z8 encore! xp f0822 series devices.
ps022517-0508 address space z8 encore! xp ? f0822 series product specification 14 data memory z8 encore! xp ? f0822 series does not use the ez8 cpu?s 64 kb data memory address space. information area table 6 describes the z8 encore! xp f0822 series information area. this 512 byte infor- mation area is accessed by setting bit 7 of the page select register to 1. when access is enabled, the information area is mapped in to the program memory and overlays the 512 bytes at addresses fe00h to ffffh . when the information area access is enabled, all reads from these program memory addresses retu rn the information area data rather than the program memory data. access to the information area is read-only. table 5. z8 encore! xp ? f0822 series program memory maps program memory address (hex) function z8f082x and z8f081x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-1fff program memory z8f042x and z8f041x products 0000-0001 option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-0fff program memory note: *see ta b l e 2 4 on page 57 for a list of the interrupt vectors. table 6. information area map program memory address (hex) function fe00h-fe3fh reserved fe40h-fe53h part number 20-character ascii alphanumeric code left justified and filled with zeros fe54h-ffffh reserved
ps022517-0508 register file address map z8 encore! xp ? f0822 series product specification 15 register file address map table 7 provides the address map for the re gister file of the z8 encore! xp ? f0822 series products. not all devices and package st yles in the f0822 se ries support the adc, the spi, or all of the gpio ports. consider registers for unimplemented peripherals as reserved. table 7. register file address map address (hex) register description mnemonic reset (hex) page no general purpose ram 000-3ff general-purpose register file ram ? xx 400-eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 78 f01 timer 0 low byte t0l 01 78 f02 timer 0 reload high byte t0rh ff 79 f03 timer 0 reload low byte t0rl ff 79 f04 timer 0 pwm high byte t0pwmh 00 79 f05 timer 0 pwm low byte t0pwml 00 79 f06 timer 0 control 0 t0ctl0 00 81 f07 timer 0 control 1 t0ctl1 00 81 timer 1 f08 timer 1 high byte t1h 00 78 f09 timer 1 low byte t1l 01 78 f0a timer 1 reload high byte t1rh ff 79 f0b timer 1 reload low byte t1rl ff 79 f0c timer 1 pwm high byte t1pwmh 00 79 f0d timer 1 pwm low byte t1pwml 00 79 f0e timer 1 control 0 t1ctl0 00 81 f0f timer 1 control 1 t1ctl1 00 81 f10-f3f reserved ? xx uart 0 f40 uart0 transmit data u0txd xx 100 uart0 receive data u0rxd xx 101 f41 uart0 status 0 u0stat0 0000011xb 101 f42 uart0 control 0 u0ctl0 00 103 f43 uart0 control 1 u0ctl1 00 103 f44 uart0 status 1 u0stat1 00 101 f45 uart0 address compare register u0addr 00 105 f46 uart0 baud rate high byte u0brh ff 106 xx=undefined
ps022517-0508 register file address map z8 encore! xp ? f0822 series product specification 16 f47 uart0 baud rate low byte u0brl ff 106 f48-f4f reserved ? xx i 2 c f50 i 2 c data i2cdata 00 139 f51 i 2 c status i2cstat 80 140 f52 i 2 c control i2cctl 00 141 f53 i 2 c baud rate high byte i2cbrh ff 143 f54 i 2 c baud rate low byte i2cbrl ff 143 f55 i 2 c diagnostic state i2cdst xx000000b 143 f56 i 2 c diagnostic control i2cdiag 00 145 f57-f5f reserved ? xx serial peripheral interface (spi) unavailable in 20-pin package devices f60 spi data spidata 01 121 f61 spi control spictl 00 122 f62 spi status spistat 00 123 f63 spi mode spimode 00 124 f64 spi diagnostic state spidst 00 125 f65 reserved ? xx f66 spi baud rate high byte spibrh ff 125 f67 spi baud rate low byte spibrl ff 125 f68-f6f reserved ? xx analog-to-digital converter (adc) f70 adc control adcctl 20 150 f71 reserved ? xx f72 adc data high byte adcd_h xx 151 f73 adc data low bits adcd_l xx 151 f74-fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 61 fc1 irq0 enable high bit irq0enh 00 63 fc2 irq0 enable low bit irq0enl 00 63 fc3 interrupt request 1 irq1 00 62 fc4 irq1 enable high bit irq1enh 00 64 fc5 irq1 enable low bit irq1enl 00 64 fc6 interrupt request 2 irq2 00 63 fc7 irq2 enable high bit irq2enh 00 65 fc8 irq2 enable low bit irq2enl 00 65 fc9-fcc reserved ? xx fcd interrupt edge select irqes 00 67 table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page no xx=undefined
ps022517-0508 register file address map z8 encore! xp ? f0822 series product specification 17 fce reserved ? 00 fcf interrupt control irqctl 00 67 gpio port a fd0 port a address paaddr 00 50 fd1 port a control pactl 00 51 fd2 port a input data pain xx 54 fd3 port a output data paout 00 55 gpio port b fd4 port b address pbaddr 00 50 fd5 port b control pbctl 00 51 fd6 port b input data pbin xx 54 fd7 port b output data pbout 00 55 gpio port c fd8 port c address pcaddr 00 50 fd9 port c control pcctl 00 51 fda port c input data pcin xx 54 fdb port c output data pcout 00 55 fdc-fef reserved ? xx watchdog timer (wdt) ff0 watchdog timer co ntrol wdtctl xxx00000b 86 ff1 watchdog timer reload upper byte wdtu ff 87 ff2 watchdog timer reload high byte wdth ff 87 ff3 watchdog timer reload low byte wdtl ff 87 ff4-ff7 reserved ? xx flash memory controller ff8 flash control fctl 00 159 ff8 flash status fstat 00 160 ff9 page select fps 00 160 ff9 (if enabled) flash sector protect fprot 00 161 ffa flash programming frequency high byte ffreqh 00 161 ffb flash programming frequency low byte ffreql 00 161 read-only memory ff8 reserved ? xx ff9 page select rps 00 160 ffa-ffb reserved ? xx ez8 cpu table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page no xx=undefined
ps022517-0508 register file address map z8 encore! xp ? f0822 series product specification 18 ffc flags ? xx refer to ez8 cpu user manual ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page no xx=undefined
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 19 control register sum- mary timer 0 high byte t0h (f00h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 current count value timer 0 low byte t0l (f01h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 current count value timer 0 reload high byte t0rh (f02h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 reload value [15:8] timer 0 reload low byte t0rl (f03h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 reload value [7:0] timer 0 pwm high byte t0pwmh (f04h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 0 pwm value [15:8] timer 0 control 0 t0ctl0 (f06h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 0 input signal is gpio pin 1 = timer 0 input signal is timer 1 out reserved timer 0 control 1 t0ctl1 (f07h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/ou tput polarity operation of this bit is a function of the current operating mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled timer 1 high byte t1h (f08h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 current count value timer 1 low byte t1l (f09h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 current count value timer 1 reload high byte t1rh (f0ah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 reload value [15:8]
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 20 timer 1 reload low byte t1rl (f0bh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 reload value [7:0] timer 1 pwm high byte t1pwmh (f0ch - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 pwm value [15:8] timer 1 pwm low byte t1pwml (f0dh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer 1 pwm value [7:0] timer 1 control 0 t1ctl0 (f0eh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved cascade timer 0 = timer 1 input signal is gpio pin 1 = timer 1 input signal is timer 0 out reserved timer 1 control 1 t1ctl1 (f0fh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode prescale value 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 timer input/ou tput polarity operation of this bit is a function of the current operating mode of the timer timer enable 0 = timer is disabled 1 = timer is enabled uart0 transmit data u0txd (f40h - write only) d7 d6 d5 d4 d3 d2 d1 d0 uart0 transmitter data byte uart0 receive data u0rxd (f40h - read only) d7 d6 d5 d4 d3 d2 d1 d0 uart0 receiver data byte
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 21 uart0 status 0 u0stat0 (f41h - read only) d7 d6 d5 d4 d3 d2 d1 d0 cts signal returns the level of the cts signal transmitter empty 0 = data is currently transmitting 1 = transmission is complete transmitter data register 0 = transmit data register is full 1 = transmit data register is empty break detect 0 = no break occurred 1 = a break occurred framing error 0 = no framing error occurred 1 = a framing occurred overrun error 0 = no overrrun error occurred 1 = an overrun error occurred parity error 0 = no parity error occurred 1 = a parity error occurred receive data available 0 = receive data register is empty 1 = a byte is available in the receive data register uart0 control 0 u0ctl0 (f42h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 loop back enable 0 = normal operation 1 = transmit data is looped back to the receiver stop bit select 0 = transmitter sends 1 stop bit 1 = transmitter sends 2 stop bits send break 0 = no break is sent 1 = output of the transmitter is zero parity select 0 = even parity 1 = odd parity parity enable 0 = parity is disabled 1 = parity is enabled cts enable 0 = cts signal has no effect on the transmitter 1 = uart recognizes cts signal as a transmit enable control signal receive enable 0 = receiver disabled 1 = receiver enabled transmit enable 0 = transmitter disabled 1 = transmitter enabled
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 22 uart0 control 1 u0ctl1 (f43h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 infrared encoder/decoder 0 = infrared endec is disabled 1 = infrared endec is enabled received data interrupt 0 = received data and errors generate interrupt requests 1 = only errors generate interrupt requests. received data does not. baud rate registers control see uart chapter for operation driver enable polarity 0 = de signal is active high 1 = de signal is active low multiprocessor bit transmit 0 = send a 0 as the multiprocessor bit 1 = send a 1 as the multiprocessor bit multiprocessor mode [0] see multiprocessor mode [1] below multiprocessor (9-bit) enable 0 = multiprocessor mode is disabled 1 = multiprocessor mode is enabled multiprocessor mode [1] with multiprocess mode bit 0: 00 = interrupt on all received bytes 01 = interrupt only on address bytes 10 = interrupt on address match and following data 11 = interrupt on data following an address match
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 23 uart0 status 1 u0stat1 (f44h- read only) d7 d6 d5 d4 d3 d2 d1 d0 mulitprocessor receive returns value of last multiprocessor bit new frame 0 = current byte is not start of frame 1 = current byte is start of new frame reserved uart0 address compare u0addr (f45h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 address compare uart0 baud rate generator high byte u0brh (f46h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 baud rate divisor uart0 baud rate generator low byte u0brl (f47h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 uart0 baud rate divisor i2c data i2cdata (f50h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c data [7:0] i2c status i2cstat (f51h - read only) d7 d6 d5 d4 d3 d2 d1 d0 nack interrupt 0 = no action required to service nak 1 = start/stop not set after nak data shift state 0 = data is not being transferred 1 = data is being transferred transmit address state 0 = address is not being transferred 1 = address is being transferred read 0 = write operation 1 = read operation 10-bit address 0 = 7-bit address being transmitted 1 = 10-bit address being transmitted acknowledge 0 = acknowledge not transmitted/received 1 = for last byte, acknowledge was transmitted/received receive data register full 0 = i2c has not received data 1 = data register contains received data transmit data register empty 0 = data register is full 1 = data register is empty
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 24 i2c control i2cctl (f52h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c signal filter enable 0 = digital filtering disabled 1 = low-pass digital filters enabled on sda and scl input signals flush data 0 = no effect 1 = clears i2c data register send nak 0 = do not send nak 1 = send nak after next byte received from slave enable tdre interrupts 0 = do not generate an interrupt when the i2c data register is empty 1 = generate an interrupt when the i2c transmit data register is empty baud rate generator 0 = interrupts behave as set by i2c control 1 = brg generates an interrupt when it counts down to zero send stop condition 0 = do not issue stop condition after data transmission is complete 1 = issue stop condition after data transmission is complete send start condition 0 = do not send start condition 1 = send start condition i2c enable 0 = i2c is disabled 1 = i2c is enabled
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 25 i2c baud rate generator high byte i2cbrh (f53h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c baud rate divisor [15:8] i2c baud rate generator low byte i2cbrl (f54h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 i2c baud rate divisor [7:0] spi data spidata (f60h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi data [7:0] spi control spictl (f61h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi enable 0 = spi disabled 1 = spi enabled master mode enabled 0 = spi configured in slave mode 1 = spi configured in master mode wire-or (open-drain) mode 0 = spi signals not configured for open-drain 1 = spi signals (sck, ss , miso, and mosi) configured for open-drain clock polarity 0 = sck idles low 1 = spi idles high phase select sets the phase relationship of the data to the clock. brg timer interrupt request 0 = brg timer function is disabled 1 = brg time-out interrupt is enabled start an spi interrupt request 0 = no effect 1 = generate an spi interrupt request interrupt re quest enable 0 = spi interrupt requests are disabled 1 = spi interrupt requests are enabled
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 26 spi status spistat (f62h - read only) d7 d6 d5 d4 d3 d2 d1 d0 slave select 0 = if slave, ss pin is asserted 1 = if slave, ss pin is not asserted transmit status 0 = no data transmission in progress 1 = data transmission now in progress reserved slave mode transaction 0 = no slave mode transaction abort detected 1 = slave mode transaction abort was detected collision 0 = no multi-master collision detected 1 = multi-master collision was detected overrun 0 = no overrun error detected 1 = overrun error was detected interrupt request 0 = no spi interrupt request pending 1 = spi interrupt request is pending spi mode spimode (f63h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 slave select value if master and spimode[1] = 1: 0 = ss pin driven low 1 = ss pin driven high slave select i/o 0 = ss pin configured as an input 1 = ss pin configured as an output (master mode only) number of data bits per 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits 111 = 7 bits diagnostic mode control 0 = reading from spibrh, spibrl returns reload values 1 = reading from spibrh, spibrl returns current brg count value reserved
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 27 spi diagnostic state spidst (f64h - read only) d7 d6 d5 d4 d3 d2 d1 d0 spi state transmit clock enable 0 = internal transmit clock enable signal is deasserted 1 = internal transmit clock enable signal is asserted shift clock enable 0 = internal shift clock enable signal is deasserted 1 = internal shift clock enable signal is asserted spi baud rate generator high byte spibrh (f66h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi baud rate divisor [15:8] spi baud rate generator low byte spibrl (f67h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 spi baud rate divisor [7:0]
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 28 adc control adcctl (f70h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 analog input select 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 0101 through 21111 = reserved continuous mode select 0 = single-shot conversion 1 = continuous conversion external vref select 0 = internal voltage reference selected 1 = external voltage reference selected reserved conversion enable 0 = conversion is complete 1 = begin conversion adc data high byte adcd_h (f72h - read only) d7 d6 d5 d4 d3 d2 d1 d0 adc data [9:2] adc data low bits adcd_l (f73h - read only) d7 d6 d5 d4 d3 d2 d1 d0 reserved adc data [1:0]
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 29 interrupt request 0 irq0 (fc0h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc interrupt request spi interrupt request i2c interrupt request uart 0 transmitter interrupt uart 0 receiver interrupt timer 0 interrupt request timer 1 interrupt request reserved for all of the above peripherals: 0 = peripheral irq is not pending 1 = peripheral irq is awaiting service irq0 enable high bit irq0enh (fc1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc irq enable hit bit spi irq enable high bit i2c irq enable high bit uart 0 transmitter irq uart 0 receiver irq enable timer 0 irq enable high bit timer 1 irq enable high bit reserved
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 30 irq0 enable low bit irq0enl (fc2h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 adc irq enable hit bit spi irq enable low bit i2c irq enable low bit uart 0 transmitter irq uart 0 receiver irq enable timer 0 irq enable low bit timer 1 irq enable low bit reserved interrupt request 1 irq1 (fc3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a pin interrupt request 0 = irq from corresponding pin [7:0] is not pending 1 = irq from corresponding pin [7:0] is awaiting service irq1 enable high bit irq1enh (fc4h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a pin irq enable high irq1 enable low bit irq1enl (fc5h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a pin irq enable low
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 31 interrupt request 2 irq2 (fc6h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin interrupt request 0 = irq from corresponding pin [3:0] is not pending 1 = irq from corresponding pin [3:0] is awaiting service reserved irq2 enable high bit irq2enh (fc7h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin irq enable high reserved irq2 enable low bit irq2enl (fc8h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c pin irq enable low reserved interrupt control irqctl (fcfh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved interrupt request enable 0 = interrupts are disabled 1 = interrupts are enabled
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 32 port a address paaddr (fd0h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open- drain) 04h = high drive enable 05h = stop mode recovery enable 06h = pull-up enable 07h-ffh = no function port a control pactl (fd1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a control[7:0] provides access to port sub-registers port a input data pain (fd2h - read only) d7 d6 d5 d4 d3 d2 d1 d0 port a input data [7:0] port a output data paout (fd3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port a output data [7:0]
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 33 port b address pbaddr (fd4h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open- drain) 04h = high drive enable 05h = stop mode recovery enable 06h = pull-up enable 07h-ffh = no function port b control pbctl (fd5h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b control [4:0] provides access to port sub-registers reserved port b input data pbin (fd6h - read only) d7 d6 d5 d4 d3 d2 d1 d0 port b input data [4:0] reserved port b output data pbout (fd7h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port b output data [4:0] reserved
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 34 port c address pcaddr (fd8h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c address[7:0] selects port sub-registers: 00h = no function 01h = data direction 02h = alternate function 03h = output control (open- drain) 04h = high drive enable 05h = stop mode recovery enable 06h = pull-up enable 07h-ffh = no function port c control pcctl (fd9h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c control [5:0] provides access to port sub-registers reserved port c input data pcin (fdah - read only) d7 d6 d5 d4 d3 d2 d1 d0 port c input data [5:0] reserved port c output data pcout (fdbh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 port c output data [5:0] reserved
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 35 watchdog timer control wdtctl (ff0h - read only) d7 d6 d5 d4 d3 d2 d1 d0 sm configuration indicator reserved ext 0 = reset not generated by reset pin 1 = reset generated by reset pin wdt 0 = wdt timeout has not occurred 1 = wdt timeout occurred stop 0 = smr has not occurred 1 = smr has occurred por 0 = por has not occurred 1 = por has occurred watchdog timer reload upper byte wdtu (ff1h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [23:16] watchdog timer reload middle byte wdth (ff2h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [15:8] watchdog timer reload low byte wdtl (ff3h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 wdt reload value [7:0]
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 36 flash control fctl (ff8h - write only) d7 d6 d5 d4 d3 d2 d1 d0 flash command 73h = first unlock command 8ch = second unlock command 95h = page erase command 63h = mass erase command 5eh = flash sector protect reg select flash status fstat (ff8h - read only) d7 d6 d5 d4 d3 d2 d1 d0 flash controller status 00_0000 = flash controller locked 00_0001 = first unlock received 00_0010 = second unlock received 00_0011 = flash controller unlocked 00_0100 = flash sector protect register selected 00_1xxx = programming in progress 01_0xxx = page erase in progress 10_0xxx = mass erase in progress reserved page select fps (ff9h - read/write) d7 d6 d5 d4 d3 d2 d1 d0 page select [6:0] identifies the flash memory page for page erase operation. information area enable
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 37 flash sector protect fprot (ff9h - read/write to 1?s) d7 d6 d5 d4 d3 d2 d1 d0 flash sector protect [7:0] 0 = sector can be programmed or erased from user code 1 = sector is protected and cannot be programmed or erased from user code flash frequency high byte ffreqh (ffah - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash frequency value [15:8] flash frequency low byte ffreql (ffbh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 flash frequency value [7:0] flags flags (ffch - read/write) d7 d6 d5 d4 d3 d2 d1 d0 f1 - user flag 1 f2 - user flag 2 h - half carry d - decimal adjust v - overflow flag s - sign flag z - zero flag c - carry flag register pointer rp (ffdh- read/write) d7 d6 d5 d4 d3 d2 d1 d0 working register page
ps022517-0508 control register summary z8 encore! xp ? f0822 series product specification 38 working register group stack pointer high byte sph (ffeh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer [15:8] stack pointer low byte spl (fffh - read/write) d7 d6 d5 d4 d3 d2 d1 d0 stack pointer [7:0] register pointer rp (ffdh- read/write) d7 d6 d5 d4 d3 d2 d1 d0
ps022517-0508 reset and stop mode recovery z8 encore! xp ? f0822 series product specification 39 reset and stop mode recovery the reset controller within the z8 encore! xp ? f0822 series controls reset and stop mode recovery operation. in typical operat ion, the following events cause a reset to occur: ? power-on reset (por) ? voltage brownout ? wdt time-out (when configured throug h the wdt_res option bit to initiate a reset) ? external reset pin assertion ? on-chip debugger initiated reset (ocdctl[0] set to 1) when the z8 encore! xp f0822 series device is in stop mode, a stop mode recovery is initiated by any of th e following events: ? wdt time-out ? gpio port input pin transition on an enabled stop mode recovery source ? dbg pin driven low reset types z8 encore! xp f0822 series provides two ty pes of reset operation (system reset and stop mode recovery). the type of reset is a function of both the current operating mode of the z8 encore! xp f0822 series devi ce and the source of the reset. table 8 lists the types of resets and their operating characteristics. table 8. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as applicable) reset 66 wd t oscillator cycles + 16 system clock cycles stop mode recovery unaffected, except wdt_ctl register reset 66 wdt oscillator cycles + 16 system clock cycles
ps022517-0508 reset and stop mode recovery z8 encore! xp ? f0822 series product specification 40 system reset during a system reset, a z8 encore! xp ? f0822 series device is held in reset for 66 cycles of the wdt oscillator followed by 16 cy cles of the system clock. at the beginning of reset, all gpio pins are configured as i nputs. all gpio programm able pull-ups are dis- abled. during reset, the ez8 cpu and the on-chip pe ripherals are idle; however, the on-chip crystal oscillator and wdt oscilla tor continue to run. the sy stem clock begins operating following the wdt oscillator cy cle count. the ez8 cpu and on-chip peripherals remain idle through all the 16 cycl es of the system clock. upon reset, control registers within the regi ster file which have a defined reset value are loaded with their reset values. other cont rol registers (including the stack pointer, register pointer, and flags) and general-pu rpose ram are undefined following the reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counte r. program execution begins at the reset vec- tor address. reset sources table 9 lists the reset sources as a function of the operating mode. the text following provides more detailed information on the individual reset sources. a por/vbo event always has priority over all other possible reset sour ces to insure a full system reset occurs. table 9. reset sources and resulting reset type operating mode reset source reset type normal or halt modes por/vbo system reset wdt time-out when configured for reset system reset reset pin assertion system reset ocd initiated reset (ocdctl[0] set to 1) system reset except the ocd is unaffected by the reset stop mode por/ vbo system reset reset pin assertion system reset dbg pin driven low system reset note:
ps022517-0508 reset and stop mode recovery z8 encore! xp ? f0822 series product specification 41 power-on reset each device in the z8 encore! xp ? f0822 series contains an internal por circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the por counter is enabled and counts 66 cycles of the wdt oscillator. after the por counte r times out, the xtal counter is enabled to count a total of 16 system clock pul ses. the device is held in the re set state until both the por counter and xtal counter have timed out. after the z8 encore! xp f0822 se ries device exits the por state, the ez8 cpu fetches th e reset vector. following por, the por status bit in the watchdog timer control register (wdtctl) is set to 1. figure 6 displays por operation. see electrical characteristics for por threshold voltage (v por ). figure 6. power-on reset operation voltage brownout reset the devices in z8 encore! xp f0822 series provide low voltage brownout protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage v cc = 0.0 v v cc = 3.3 v v por v vbo primary oscillator internal reset signal program execution oscillator start-up xtal wdt clock por counter delay counter delay not to scale
ps022517-0508 reset and stop mode recovery z8 encore! xp ? f0822 series product specification 42 remains below the por voltage threshold (v por ), the vbo block holds the device in the reset state. after the supply voltage again exceeds the por voltage threshold, the device progresses through a full system reset se quence as described in the por section. following por, the por status bit in the watchdog timer control register (wdtctl) is set to 1. figure 7 displays the vbo operation. see electrical characteristics on page 185 for the vbo and por threshold voltages (v vbo and v por ). the vbo circuit can be either enabled or di sabled during stop mode. operation during stop mode is set by the vbo_ao option bit. for info rmation on configuring vbo_ao, see option bits on page 163. figure 7. voltage brownout reset operation watchdog timer reset if the device is in normal or halt mode, wd t initiates a system reset at time-out, if the wdt_res option bit is set to 1. this is th e default (unprogrammed) setting of the wdt_res option bit. the wdt status bit in the wdt contro l register is set to signify that the reset was initiated by the wdt. v cc = 3.3 v v por vvbo internal reset signal program execution program execution voltage brownout v cc = 3.3 v primary oscillator wdt clock xtal por counter delay counter delay
ps022517-0508 reset and stop mode recovery z8 encore! xp ? f0822 series product specification 43 external pin reset the reset pin contains a schmitt-triggered input, an internal pull-up , an analog filter, and a digital filter to reject noise. after the reset pin is asserted for at least 4 system clock cycles, the device prog resses through the system r eset sequence. while the reset input pin is asserted low, z8 encore! xp f0822 series device continues to be held in the reset state. if the reset pin is held low beyond the sy stem reset time-out, the device exits the reset state immediately following reset pin deassertion. following a system reset initiated by the external reset pin, the ext status bit in the watchdog timer con- trol register (wdtctl) is set to 1. on-chip debugger initiated reset a por is initiated using the ocd by setting the rst bit in the ocd control register. the ocd block is not reset but the rest of the chip goes through a normal system reset. the rst bit automatically clears du ring the system r eset. following the system reset, the por bit in the wdt control register is set. stop mode recovery stop mode is entered by execution of a stop instruction by the ez8 cpu. for detailed information on stop mode, see low-power modes on page 45. during stop mode recovery, the device is held in reset for 66 cycles of th e wdt oscillator followed by 16 cycles of the system clock. stop mode reco very only affects the contents of the wdt control register and does not affect an y other values in the register file, including the stack pointer, re gister pointer, flags, periph eral control registers, and general-purpose ram. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program coun ter. program execution begins at the reset vector address. following stop mode recovery, the stop bit in the wdt control register is set to 1. table 10 lists the stop mode recovery sources and resulting actions. the text following provides mo re detailed information on ea ch of the stop mode recov- ery sources. table 10. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode wdt time-out when configured for reset stop mode recovery wdt time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery
ps022517-0508 reset and stop mode recovery z8 encore! xp ? f0822 series product specification 44 stop mode recovery using wdt time-out if the wdt times out during stop mode, the device undergoes a stop mode recovery sequence. in the wdt control register, the wdt and stop bits are set to 1. if the wdt is configured to generate an interrupt upon time-out and the z8 encore! xp ? f0822 series device is configured to r espond to interrupts, the ez8 cpu services the wdt interrupt request following the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins can be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recove r source, a change in the input pin value (from high to low or from low to high) initia tes stop mode recovery. the gpio stop mode recovery signals are filtered to reject pul ses less than 10 ns (typical) in duration. in the wdt control register, the stop bit is set to 1. in stop mode, the gpio port input data registers (pxin) are disabled. the port input data registers record the port tran sition only if the signal stays on the port pin through the end of the stop mode r ecovery delay. therefore, short pulses on the port pin initiates stop mode recovery without being written to the port input data register or without initiating an interrupt (if enabled for that pin). caution:
ps022517-0508 low-power modes z8 encore! xp ? f0822 series product specification 45 low-power modes z8 encore! xp ? f0822 series products contain power-saving features. the highest level of power reduction is provided by stop mode. the next level of power reduction is pro- vided by the halt mode. stop mode execution of the ez8 cpu?s stop instructio n places the device into stop mode. in stop mode, the operating characteristics are: ? primary crystal oscillator is stopped; the xi n pin is driven high and the xout pin is driven low. ? system clock is stopped. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? if enabled for operation in stop mode, the wdt and its internal rc oscillator continue to operate. ? if enabled for operation in stop mode through the associated option bit, the vbo protection circuit continues to operate. ? all other on-chip peripherals are idle. to minimize current in stop mode, wdt must be disabled and all gpio pins configured as digital inputs must be driven to one of the supply rails (v cc or gnd). the device can be brought out of stop mode using stop mode recovery. for more information on stop mode recovery, see reset and stop mode recovery on page 39. stop mode must not be used when drivi ng the z8f082x family devices with an ex- ternal clock driver source. halt mode execution of the ez8 cpu?s halt instructio n places the device into halt mode. in halt mode, the operating characteristics are: ? primary crystal oscillator is en abled and continues to operate. ? system clock is enabled and continues to operate. ? ez8 cpu is stopped. ? program counter st ops incrementing. caution:
ps022517-0508 low-power modes z8 encore! xp ? f0822 series product specification 46 ? wdt?s internal rc oscillator continues to operate. ? if enabled, the wdt continues to operate. ? all other on-chip peripherals continue to operate. the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? wdt time-out (interrupt or reset) ? power-on reset ? voltage brownout reset ? external reset pin assertion to minimize current in halt mode, all gpio pi ns which are configured as inputs must be driven to one of the supply rails (v cc or gnd).
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 47 general-purpose input/output z8 encore! xp ? f0822 series products support a maximum of 19 port pins (ports a?c) for general-purpose input/output (gpio) operations. each port consists control and data registers. the gpio control registers are used to determine data di rection, open-drain, output drive current, programmable pull-ups, stop mode recovery functionality, and alternate pin functions. each port pin is indi vidually programmable. ports a and c support 5 v-tolerant inputs. gpio port availability by device table 11 lists the port pins available w ith each device and package type. architecture figure 8 displays a simplified block diagram of a gpio port pin. it does not display the ability to accommodate alternat e functions, variable port cu rrent drive strength, and pro- grammable pull-up. gpio alternate functions many of the gpio port pins are used as both general-purpose i/o and to provide access to on-chip peripheral functions such as timer s and serial communication devices. the port a?c alternate function sub-registers conf igure these pins for either general-purpose i/o or alternate function operation. when a pin is configured for alte rnate function, control of the port-pin direction (input/output) is passed from the port a?c data direction registers to the alternate function assigned to this pin. table 12 lists the alternate functions associated with each port pin. table 11. port availability by device and package type devices package port a port b port c z8x0821, z8x0811, z8x0421, z8x0411 20-pin [7:0] [1:0] [0] z8x0822, z8x0812, z8x0422, z8x0412 28-pin [7:0] [4:0] [5:0]
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 48 figure 8. gpio port pin block diagram table 12. port alternate function mapping port pin mnemonic alternate function description port a pa0 t0in timer 0 input pa1 t0out timer 0 output pa2 de uart 0 driver enable pa3 cts0 uart 0 clear to send pa4 rxd0 / irrx0 uart 0 / irda 0 receive data pa5 txd0 / irtx0 uart 0 / irda 0 transmit data pa6 scl i 2 c clock (automatically open-drain) pa7 sda i 2 c data (automatically open-drain) port b pb0 ana0 adc analog input 0 pb1 ana1 adc analog input 1 pb2 ana2 adc analog input 2 pb3 ana3 adc analog input 3 pb4 ana4 adc analog input 4 d q dq d q gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt-trigger
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 49 gpio interrupts many of gpio port pins are used as interrupt sources. some port pins are configured to generate an interrupt request on either the ri sing edge or falling edge of the pin input signal. other port pin interrupt s generate an interrupt when any edge occurs (both rising and falling). for more details on in terrupts using the gpio pins, see gpio port pin block diagram on page 48. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 13 lists the gpio port registers and sub- registers. use the port a?c address and control registers together to provide access to sub-registers for port configuration and control. port c pc0 t1in timer 1 input pc1 t1out timer 1 output pc2 ss spi slave select pc3 sck spi serial clock pc4 mosi spi master out slave in pc5 miso spi master in slave out table 13. gpio port registers and sub-registers port register mnemonic port register name p x addr port a?c address register (selects sub-registers) p x ctl port a?c control register (provides access to sub-registers) p x in port a?c input data register p x out port a?c output data register port sub-register mnemonic port register name p x dd data direction p x af alternate function table 12. port alternate function mapping (continued) port pin mnemonic alternate function description
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 50 port a?c address registers the port a?c address registers select the gpio port functionality accessible through the port a?c control registers. the port a? c address and control registers combine to provide access to all gpio port control ( table 14 ). paddr[7:0]?port address the port address selects one of the sub-re gisters accessible through the port control register. p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recovery source enable p x pue pull-up enable table 14. port a?c gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/w addr fd0h, fd4h, fd8h paddr[7:0] port control sub-register a ccessible using the port a?c control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction 02h alternate function 03h output control (open-drain) 04h high drive enable 05h stop mode recove ry source enable 06h pull-up enable 07h?ffh no function table 13. gpio port registers and sub-registers (continued) port register mnemonic port register name
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 51 port a?c control registers the port a?c control registers set the gpio port operation. the value in the correspond- ing port a?c address register determines th e control sub-registers accessible using the port a?c control register ( table 15 ). pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. port a?c data direction sub-registers the port a?c data direction sub-register is accessed through the port a?c control register by writing 01h to the port a?c address register ( table 16 ). dd[7:0]?data direction these bits control the direction of the ass ociated port pin. port alternate function operation overrides the data direction register setting. 0 = output. data in the port a?c output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and th e value written into the port a?c input data register. the output driver is tri-stated. port a?c alternate function sub-registers the port a?c alternate function sub-register ( table 17 ) is accessed through the port a?c control register by writing 02h to the port a?c address register. the port a?c alternate function sub-registers sel ect the alternate functions for the selected table 15. port a?c control registers (p x ctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/w addr fd1h, fd5h, fd9h table 16. port a?c data direction sub-registers bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 1 r/w r/w addr if 01h in port a?c address register, access ible through the port a?c control register
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 52 pins.to determine the alternate function associated with each port pin, see gpio port pin block diagram on page 48. do not enable alternate functio n for gpio port pins which do not have an associated alternate function. failure to follow this guidelin e can result in unpr edictable operation. af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?c data direction sub-register determines the direction of the pin. 1 = the alternate function is selected. po rt pin operation is controlled by the alternate function. port a?c output control sub-registers the port a?c output control sub-register ( table 18 ) is accessed through the port a?c control register by writing 03h to the port a?c address register. setting the bits in the port a?c output control sub-registers to 1 configures the specified port pins for open-drain operation. these sub-registers af fect the pins directly and, as a result, alternate functions are also affected. poc[7:0]?port output control these bits function independently of the a lternate function bit and always disable the drains if set to 1. 0 = the drains are enabled for any ou tput mode (unless overridden by the table 17. port a?ca?c alternate function sub-registers bits 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 0 r/w r/w addr if 02h in port a?c address register, access ible through the port a?c control register table 18. port a?c output control sub-registers bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 0 r/w r/w addr if 03h in port a?c address register, access ible through the port a?c control register caution:
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 53 alternate function). 1 = the drain of the associated pin is disabled (open-drain mode). port a?c high drive enable sub-registers the port a?c high drive enable sub-register ( table 19 ) is accessed through the port a?c control register by writing 04h to the port a?c addres s register. setting the bits in the port a?c high drive enable sub -registers to 1 configur es the specified port pins for high current output drive operation. the port a?c high drive enable sub-register affects the pins directly and, as a resu lt, alternate functions are also affected. phde[7:0]?port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a?c stop mode recovery source enable sub-registers the port a?c stop mode recovery source enable sub-register ( table 20 ) is accessed through the port a?c cont rol register by writing 05h to the port a?c address register. setting the bits in the port a?c stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a st op mode recovery source. transitions on this pin during stop mode does not initiate stop mode recovery. table 19. port a?c high drive enable sub-registers bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 0 r/w r/w addr if 04h in port a?c address register, access ible through the port a?c control register table 20. port a?c stop mode recovery source enable sub-registers bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 0 r/w r/w addr if 05h in port a?c address register, access ible through the port a?c control register
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 54 1 = the port pin is configured as a stop mode recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. port a?c pull-up enable sub-registers the port a?c pull-up en able sub-register ( table 21 ) is accessed through the port a?c control register by writing 06h to the port a?c address register. setting the bits in the port a?c pull-up enable sub-re gisters enables a weak internal resistive pull-up on the specified port pins. ppue[7:0]?port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. port a?c input data registers reading from the port a?c input data registers ( table 22 ) returns the sampled values from the corresponding port pi ns. the port a?c input data registers are read-only. pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). table 21. port a?c pull-up enable sub-registers bits 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 0 r/w r/w addr if 06h in port a?c address register, access ible through the port a?c control register table 22. port a?c input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset x r/w r addr fd2h, fd6h, fdah
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 55 port a?c output data register the port a?c output data register ( table 23 ) controls the output data to the pins. pout[7:0]?port output data these bits contain the data to be driven to th e port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1 = drive a logical 1 (high). high value is no t driven if the drain has been disabled by setting the corresponding po rt output control register bit to 1. table 23. port a?c output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 0 r/w r/w addr fd3h, fd7h, fdbh
ps022517-0508 general-purpose input/output z8 encore! xp ? f0822 series product specification 56
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 57 interrupt controller the interrupt controller on z8 encore! xp ? f0822 series products prioritizes the interrupt requests from the on-chip peripherals and the gp io port pins. the features of the interrupt controller include the following: ? 19 unique interrupt vectors: ? 12 gpio port pin interrupt sources. ? 7 on-chip peripheral interrupt sources. ? flexible gpio interrupts: ? 8 selectable rising and falling edge gpio interrupts. ? 4 dual-edge interrupts. ? three levels of individually pr ogrammable interrupt priority. ? wdt is configured to generate an interrupt. interrupt requests (irqs) allow peripheral devices to suspend cpu operation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this isr is involved with the exch ange of data, status informa tion, or control information between the cpu and the interrupting pe ripheral. when the service routine is completed, the cpu returns to the op eration from which it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt control has no effect on operatio n. for more informatio n on interrupt servic- ing, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . interrupt vector listing table 24 lists all the interrupts available in order of priority. the interrupt vector is stored with the most significant byte (msb) at th e even program memory address and the least significant byte (lsb) at the follo wing odd program memory address. table 24. interrupt vectors in order of priority priority program memory vector address interrupt source highest 0002h reset (not an interrupt) 0004h wdt (see watchdog timer on page 83) 0006h illegal instruction trap (not an interrupt)
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 58 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h i 2 c 0014h spi 0016h adc 0018h port a7, rising or falling input edge 001ah port a6, rising or falling input edge 001ch port a5, rising or falling input edge 001eh port a4, rising or falling input edge 0020h port a3, rising or falling input edge 0022h port a2, rising or falling input edge 0024h port a1, rising or falling input edge 0026h port a0, rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c3, both input edges 0032h port c2, both input edges 0034h port c1, both input edges lowest 0036h port c0, both input edges table 24. interrupt vectors in order of priority (continued) priority program memory vector address interrupt source
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 59 architecture figure 9 displays a block diagram of the interrupt controller. figure 9. interrupt controller block diagram operation master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an ei (enable interrupt) instruction. ? execution of an iret (return from interrupt) instruction. ? writing a 1 to the irqe bit in the interrupt control register. interrupts are globally disabled by any of the following actions: ? execution of a di (disable interrupt) instruction. ? ez8 cpu acknowledgement of an interrupt se rvice request from the interrupt controller. ? writing a 0 to the irqe bit in the interrupt control register. ? reset. ? execution of a trap instruction. ? illegal instruction trap. vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 60 interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority , and level 1 is the lowest priority. if all the interrupts were enabled with identical interrupt priority (all as level 2 interrupts), then interrupt priority would be assigned fro m highest to lowest as specified in table 24 . level 3 interrupts always have higher priority than level 2 interrupts which in turn always have higher priority than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is assigned as specified in table 24 . reset, wdt interrupt (if enabled), and illegal instruction tr ap always have highest priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (single pulse). when the interrupt request is acknowledged by the ez8 cpu, the corre- sponding bit in the interrupt request register is cleared until the ne xt interrupt occurs. writing a 0 to the corresponding bit in the interrupt reques t register likewise clears the interrupt request. the following style of codi ng to clear bits in the interrupt request registers is not recommended. all incoming in terrupts received between execution of the first ldx command and the last ldx command is lost. poor coding style resulting in lost interrupt requests: ldx r0, irq0 and r0, mask ldx irq0, r0 to avoid missing interrupts, the following style of codi ng to clear bits in the interrupt request 0 register is recommended: good coding style that avoids lost interrupt requests: andx irq0, mask software interrupt assertion program code generates interrupts directly. wr iting 1 to the desired bit in the interrupt request register triggers an interrupt (ass uming that interrupt is enabled). when the interrupt request is acknowledged by the ez8 cpu, the bit in the interrupt request regis- ter is automatically cleared to 0. the following style of coding to genera te software interrupts by setting bits in the interrupt request registers is not recommended. all incoming interrupts received between execution of the first ldx command and the last ldx command is lost. caution: note: caution:
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 61 poor coding style that resulting in lost interrupt requests: ldx r0, irq0 or r0, mask ldx irq0, r0 to avoid missing interrupts, the following style of coding to set bits in the interrupt request registers is recommended good coding style that avoids lost interrupt requests: orx irq0, mask interrupt control register definitions for all interrupts other than the wdt interru pt, the interrupt control registers enable individual interrupts, set interrupt prio rities, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register ( table 25 ) stores the interru pt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register be comes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the ez8 cpu. if interrupts are globally disabled (polle d interrupts), the ez8 cpu reads the irq0 register to determine if any interrupt requests are pending. reserved?must be 0 t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. table 25. interrupt request 0 register (irq0) bits 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0txi i2ci spii adci reset 0 r/w r/w addr fc0h note:
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 62 u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the ua rt 0 transmitter is awaiting service. i 2 ci? i 2 c interrupt request 0 = no interrupt request is pending for the i 2 c. 1 = an interrupt request from the i 2 c is awaiting service. spii?spi interrupt request 0 = no interrupt request is pending for the spi. 1 = an interrupt request from the spi is awaiting service. adci?adc interrupt request 0 = no interrupt request is pending for the adc. 1 = an interrupt request from the adc is awaiting service. interrupt request 1 register the interrupt request 1 (irq1) register ( table 26 ) stores interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq1 register be comes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the ez8 cpu. if interrupts are globally disabled (polle d interrupts), the ez8 cpu reads the irq1 register to determine if any interrupt requests are pending. pa x i?port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x . 1 = an interrupt request from gpio port a pin x is awaiting service. where x indicates the specific gpio po rt pin number (0 through 7). table 26. interrupt request 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pa7i pa6i pa5i pa4i pa3i pa2i pa1i pa0i reset 0 r/w r/w addr fc3h
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 63 interrupt request 2 register the interrupt request 2 (irq2) register ( table 27 ) stores interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq2 register be comes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the ez8 cpu. if interrupts are globally disabled (polle d interrupts), the ez8 cpu reads the irq2 register to determine if any interrupt requests are pending. reserved?must be 0 pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. where x indicates the specific gpio port c pin number (0 through 3). irq0 enable high a nd low bit registers the irq0 enable high and low bit registers ( table 29 and table 30 ) form a priority encoded enabling for interrupts in the interrupt request 0 register. priority is generated by setting bits in each register. table 28 describes the priority control for irq0. table 27. interrupt request 2 register (irq2) bits 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 0 r/w r/w addr fc6h table 28. irq0 enable and priority encoding irq0enh[ x ] irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7.
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 64 reserved?must be 0 t1enh ?timer 1 interrupt request enable high bit t0enh ?timer 0 interrupt request enable high bit u0renh ?uart 0 receive interrupt request enable high bit u0tenh ?uart 0 transmit interrupt request enable high bit i2cenh ?i 2 c interrupt request enable high bit spienh ?spi interrupt request enable high bit adcenh ?adc interrupt request enable high bit reserved?must be 0 t1enl ?timer 1 interrupt request enable low bit t0enl ?timer 0 interrupt request enable low bit u0renl ?uart 0 receive interrupt request enable low bit u0tenl ?uart 0 transmit interrupt request enable low bit i2cenl ?i 2 c interrupt request enable low bit spienl ?spi interrupt request enable low bit adcenl ?adc interrupt request enable low bit irq1 enable high a nd low bit registers table 31 describes the priority control for ir q1. the irq1 enable high and low bit registers ( table 32 and table 33 ) form a priority encoded en abling for interrupts in the interrupt request 1 register. priority is generated by setting bits in each register. table 29. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0tenh i2cenh spienh adcenh reset 0 r/w r/w addr fc1h table 30. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0tenl i2cenl spienl adcenl reset 0 r/w r/w addr fc2h
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 65 pa x enh ?port a bit[ x ] interrupt request enable high bit pa x enl ?port a bit[ x ] interrupt request enable low bit irq2 enable high a nd low bit registers table 34 describes the priority control for ir q2. the irq2 enable high and low bit registers ( table 35 and table 36 ) form a priority encoded en abling for interrupts in the interrupt request 2 register. priority is generated by se tting bits in each register. table 31. irq1 enable and priority encoding irq1enh[ x ] irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7. table 32. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pa7enh pa6enh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 0 r/w r/w addr fc4h table 33. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pa7enl pa6enl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 0 r/w r/w addr fc5h
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 66 reserved?must be 0. c3enh ?port c3 interrupt request enable high bit c2enh ?port c2 interrupt request enable high bit c1enh ?port c1 interrupt request enable high bit c0enh ?port c0 interrupt request enable high bit reserved?must be 0. c3enl ?port c3 interrupt request enable low bit c2enl ?port c2 interrupt request enable low bit c1enl ?port c1 interrupt request enable low bit c0enl ?port c0 interrupt request enable low bit table 34. irq2 enable and priority encoding irq2enh[ x ] irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7. table 35. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 0 r/w r/w addr fc7h table 36. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 0 r/w r/w addr fc8h
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 67 interrupt edge select register the interrupt edge sele ct (irqes) register ( table 37 ) determines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port input pin. the minimum pulse width must be gr eater than 1 system clock to guarantee capture of the edge triggered interrupt. edge detection for pulses l ess than 1 system clock are not guaranteed. ies x ?interrupt edge select x 0 = an interrupt request is genera ted on the falling edge of the pa x input. 1 = an interrupt request is genera ted on the rising edge of the pa x input. where x indicates the specific gpio po rt pin number (0 through 7). interrupt control register the interrupt control (irqctl) register ( table 38 ) contains the master enable bit for all interrupts. irqe?interrupt request enable this bit is set to 1 by execution of an ei (enable interrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this bit. 0 = interrupts are disabled. 1 = interrupts are enabled. reserved?must be 0 table 37. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 0 r/w r/w addr fcdh table 38. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 0 r/w r/w r addr fcfh
ps022517-0508 interrupt controller z8 encore! xp ? f0822 series product specification 68
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 69 timers z8 encore! xp ? f0822 series products contain up to two 16-bit reloadable timers that can be used for timing, event counting, or gene ration of pulse-width modulated signals. the timer features include: ? 16-bit reload counter. ? programmable prescaler with prescale values from 1 to 128. ? pwm output generation. ? capture and compare capability. ? external input pin for timer input, clock ga ting, or capture signal. external input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. ? timer output pin. ? timer interrupt. in addition to the timers described in this chapter, the baud rate generators for any unused uart, spi, or i 2 c peripherals can also be u sed to provide basic timing functionality. see the respective serial communication peripheral chapters for information on using the baud rate generators as timers. architecture figure 10 displays the architecture of the timers. operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting.
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 70 figure 10. timer block diagram timer operating modes the timers are configured to op erate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte regist ers. the timer input is the sy stem clock. on reaching the reload value, the timer generates an interrupt and the count value in the timer high and low byte registers is reset to 0001h . then, the timer is automa tically disabled and stops counting. also, if the timer output alternate functio n is enabled, the timer output pin changes state for one system clock cycle (from low to high or vice-versa) on timer reload. if it is required for the timer output to make a permanent state change on one-shot time-out, first set the tpol bit in the timer control regist er to the start value before beginning one-shot mode. then, after starting the timer, set tpol to the opposite bit value. follow the steps below for configuring a timer for one-shot mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode 16-bit pwm / compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer timer block system timer data block interrupt output control bus clock input gate input capture input
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 71 ? set the prescale value ? if using the timer output alternate function, set the initial output level (high or low). 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always provides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. th e timer input is the system clock. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) upon timer reload. follow the steps below for configuring a ti mer for continuous mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode ? set the prescale value. ? if using the timer output alternate function, set the initial output level (high or low). 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this only affects the first pass in continuous mode. after the first timer reload in continuous mode, counting al ways begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. one-shot mode time-out period (s) reload value s tart value ? () xprescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------- =
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 72 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first time-out period. counter mode in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the gpio port pi n timer input alternate function. the tpol bit in the timer control register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in c ounter mode, the prescaler is disabled. the input frequency of the timer input signal must not exceed one-fourth system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt , the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below for configuring a timer for counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for counter mode. ? select either the rising edge or falling edge of the timer input signal for the count. this also sets the initial logic level (hig h or low) for the timer output alternate function. however, the timer output fu nction does not have to be enabled. 2. write to the timer high and low byte regi sters to set the starting count value. this only affects the first pass in counter mode. after the first timer reload in counter mode, counting always begins at the reset value of 0001h . generally, in counter mode the timer high and low byte registers must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. continuous mode time-out period (s) reload value x prescale system clock frequency (hz) ------------------------------------------------------------------------------- = caution:
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 73 4. if required, enable the timer interrupt and set the timer inte rrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control re gister to enable the timer. in counter mode, the number of timer input transitions since the timer start is given by the following equation: pwm mode in pwm mode, the timer output s a pulse-width modulator output signal through a gpio port pin. the timer input is th e system clock. the timer first counts up to the 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, the ti mer output toggles. the timer continues counting until it reaches the reload value stor ed in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and then transitions to a low (0) when the timer value ma tches the pwm value. the timer output signal returns to a high (1 ) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and then transitions to a high (1) when the timer value matches the pwm value. the timer output signal returns to a low (0 ) after the timer reaches the reload value and is reset to 0001h . follow the steps below for configuring a timer for pwm mode and initiating the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm mode. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . counter mode timer input transitions current count value start value ? =
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 74 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value mu st be greater than the pwm value. 5. if required, enable the timer interrupt and set the timer inte rrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is given by the following equation. if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation is used to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm output high time to the total period is given by if tpol is set to 1, the ratio of the pwm output high time to the total period is given by capture mode in capture mode, the current timer count valu e is recorded when the desired external timer input transition occurs. the capture coun t value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event occu rs, an interrupt is generated and the timer continues counting. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an interrupt and continues counting. follow the steps below for configuring a timer for capture mode and initiating the count: 1. write to the timer control register to: ? disable the timer pwm period (s) reload value x prescale system clock frequency (hz) ------------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------------- x 1 0 0 = pwm output high time ratio (%) pwm value reload value ----------------------------------- -x100 =
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 75 ? configure the timer for capture mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows user software to determine if interrupts were generated by either a capture event or a reload. if the pwm high and low byte registers still contains 0000h after the interrupt, then the interrupt was generated by a reload. 5. if required, enable the timer interrupt and set the timer inte rrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer st art to capture event is calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte regist ers. the timer input is the system clock. upon reaching the compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes stat e (from low to high or from high to low) upon compare. if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. follow the steps below for configuring a timer for compare mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode ? set the prescale value ? set the initial logic level (high or low) fo r the timer output alternate function, if required 2. write to the timer high and low byte registers to set the starting count value 3. write to the timer reload high and low byte registers to set the compare value capture elapsed time (s) capture value start value ? () xprescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- - =
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 76 4. if required, enable the timer interrupt and set the timer inte rrupt priority by writing to the relevant interrupt registers 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function 6. write to the timer control register to enable the timer and initiate counting in compare mode, the system clock al ways provides the timer input. the compare time is calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal is still asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. follow the steps below for configuring a timer for gated mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for gated mode ? set the prescale value 2. write to the timer high and low byte regi sters to set the starting count value. this only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h 3. write to the timer reload high and low byte registers to set the reload value 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers 5. configure the associated gpio port pi n for the timer input alternate function 6. write to the timer control register to enable the timer 7. assert the timer input signal to initiate the counting compare mode time (s) compare value start value ? () x prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------------- =
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 77 capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the required transition (rising edge or falling edge) is set by the tpol bit in the timer control register. the timer input is the system clock. every subsequent desired transitio n (after the first) of the timer input signal captures the current count value. the capture value is wr itten to the timer pwm high and low byte registers. when the capture even t occurs, an interrupt is gene rated, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the coun t value in the timer high and low byte registers is reset to 0001h and counting resumes. follow the steps below for configuring a timer for capture/compare mode and initi- ating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ) 3. write to the timer reload high and low byte registers to set the compare value 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers 5. configure the associated gpio port pi n for the timer input alternate function 6. write to the timer control register to enable the timer 7. counting begins on the first appropriat e transition of the timer input signal. no interrupt is genera ted by this first edge in capture/compare mode, th e elapsed time from timer start to capture event is calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when th e timer is enabled and the timer high byte capture elapsed time (s) capture value start value ? () xprescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- - =
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 78 register is read, the contents of the timer low byte register are placed in a holding register. a subsequent read from the timer lo w byte register returns the value in the holding register. this operatio n allows accurate reads of th e full 16-bit timer count value while enabled. when the timers are not enabled, a read from the timer low byte register returns the actual va lue in the counter. timer output signal operation timer output is a gpio port pin alternate func tion. generally, the time r output is toggled every time the counter is reloaded. timer control register definitions timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and txl) registers ( table 39 ) contain the current 16-bit timer count value. when the tim er is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from tmrl always returns this temporary register when the timers are enabled. when the timer is disabled, reads from the tmrl reads the register directly. writing to the timer high and low byte regi sters while the timer is enabled is not recommended. there are no temporary holdin g registers available for write operations, so simultaneous 16-bit writes are not possib le. if either the timer high or low byte registers are written during counting, the 8-bit written value is placed in the counter (high or low byte) at the next clock edge. the co unter continues counti ng from the new value. table 39. timer 0?1 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 0 r/w r/w addr f00h, f08h table 40. timer 0?1 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 01 r/w r/w addr f01h, f09h
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 79 th and tl?timer high and low bytes these 2 bytes, {tmrh[7:0], tmrl[7:0]}, cont ain the current 16-bit timer count value. timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers ( table 41 ) store a 16-bit reload value, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stored in a temporary holding re gister. when a write to the timer reload low byte register occurs, the temporary holding register value is written to the timer high byte register. this operation allows simu ltaneous updates of the 16-bit timer reload value. in compare mode, the timer reload high and low byte registers store the 16-bit compare value. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count value which in itiates a timer reload to 0001h . in compare mode, these two bytes form the 16-bit compare value. timer 0?1 pwm high and low byte registers the timer 0?1 pwm high and low byte (txpwmh and txpwml) registers ( table 43 and table 44 ) are used for pulse-width modulator (pwm) operations. these registers also store the capture values for the capture and capture/compare modes. table 41. timer 0?1 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 1 r/w r/w addr f02h, f0ah table 42. timer 0?1 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 1 r/w r/w addr f03h, f0bh
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 80 pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl) register. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. timer 0?3 control 0 registers the timer 0?3 control 0 (txctl0) registers ( table 45 ) allow cascading of the timers. csc?cascade timers 0 = timer input signal comes from the pin. 1 = for timer 0, input signal is connected to timer 1 output. for timer 1, input signal is connected to timer 0 output. table 43. timer 0?1 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 0 r/w r/w addr f04h, f0ch table 44. timer 0?1 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 0 r/w r/w addr f05h, f0dh table 45. timer 0?3 control 0 register (txctl0) bits 7 6 5 4 3 2 1 0 field reserved csc reserved reset 0 r/w r/w addr f06h, f0eh, f16h, f1eh
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 81 timer 0?1 control 1 registers the timer 0?1 control (txctl) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode. ten?timer enable 0 = timer is disabled. 1 = timer enabled to count. tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, th e timer output signal is comp lemented upon timer reload. continuous mode when the timer is disabled, the timer output signa l is set to the value of this bit. when the timer is enabled, the timer output sign al is complemented upon timer reload. counter mode if the timer is enabled the timer output si gnal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling ed ge of the timer input signal. pwm mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. table 46. timer 0?1 control register (txctl) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 0 r/w r/w addr f07h, f0fh
ps022517-0508 timers z8 encore! xp ? f0822 series product specification 82 compare mode when the timer is disabled, the timer output signa l is set to the value of this bit. when the timer is enabled, the timer output sign al is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the timer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first risi ng edge of the timer input signal. the current count is captured on subsequent rising edges of the timer input signal. 1 = counting is started on the first falling edge of the timer input signal. the current count is captured on su bsequent falling edges of the timer input signal. pres?prescale value the timer input clock is divided by 2 pres , where pres is set from 0 to 7. the prescaler is reset each time the timer is disabled. this insures proper clock di vision each time the timer is restarted. 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 tmode?timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode
ps022517-0508 watchdog timer z8 encore! xp ? f0822 series product specification 83 watchdog timer watchdog timer (wdt) protects against corrupt or unreliable software, power faults, and other system-level problems wh ich can place the z8 encore! xp ? f0822 series device into unsuitable operating states. it includes the following features: ? on-chip rc oscillator. ? a selectable time-out response?reset or interrupt. ? 24-bit programmable time-out value. operation wdt is a retriggerable one-shot timer that re sets or interrupts the z8 encore! xp f0822 series device when the wdt reaches its terminal count. it uses its own dedicated on-chip rc oscillator as its clock source. the wdt has only two modes of operation?on and off. when enabled, it always counts and mu st be refreshed to prevent a time-out. an enable is performed by executing the wdt instruction or by setting the wdt_ao option bit. the wdt_ao bit enables the wdt to operate all the time, even if a wdt instruction has not been executed. the wdt is a 24-bit reloadable downcounte r that uses three 8-bit registers in the ez8 cpu register space to set the reload va lue. the nominal wdt time-out period is given by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watchdog timer rc oscillator frequency is 10 khz. wdt cannot be refreshed once it reaches 000002h . the wdt reload value must not be set to values below 000004h . table 47 provides information on approximate time-out delays for mini mum and maximum wdt reload values. table 47. watchdog timer approximate time-out delays wdt reload value wdt reload value approximate time-out delay (with 10 khz typical wdt oscillator frequency) (hex) (decimal) typical description 000004 4 400 s minimum time-out delay ffffff 16,777,215 1677.5 s maximum time-out delay wdt time-out period (ms) wdt reload value 10 -------------------------------------------------- - =
ps022517-0508 watchdog timer z8 encore! xp ? f0822 series product specification 84 watchdog timer refresh when first enabled, the wdt is loaded with the value in th e wdt reload registers. the wdt then counts down to 000000h unless a wdt instruction is executed by the ez8 cpu. execution of the wdt instruction causes the downcounter to be reloaded with the wdt reload value stored in the wdt reload registers. counting resumes following the reload operation. when z8 encore! xp ? f0822 series device is operating in debug mode (using the ocd), the wdt is continu ously refreshed to preven t spurious wdt time-outs. watchdog timer time-out response the wdt times out when the counter reaches 000000h . a wdt time-out generates either an interrupt or a reset. the wdt_res option bit determines the time-out response of the wdt. for information regarding programming of the wdt_res option bit, see option bits on page 163. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occurs , the wdt issues an interrupt request to the interrupt controller and sets the wdt status bit in the wdt control register. if interrupts are enabled, the ez8 cpu responds to the interrupt request by fetching the wdt interrupt vector and executing the code from the vector address. after time-out and interrupt generation, the wdt counter rolls over to its maximum value of fffffh and continues counting. the wdt c ounter is not automatically re turned to its reload value. wdt reset in stop mode if enabled in stop mode and configured to ge nerate a reset when a time-out occurs and the device is in stop mode , the wdt initiates a stop mode recovery. both the wdt status bit and the stop bit in the wdt control regist er is set to 1 following the wdt time-out in stop mode. for more information, see reset and stop mode recovery on page 39. default operation is for the wd t and its rc oscillator to be enabled during stop mode. to minimize power consumption in stop mode, the wdt and its rc oscillator is disabled in stop mode. the following sequence configures the wdt to be disabled when the z8f082x family device enters stop mode following execution of a stop instruction: 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write 81h to the watchdog timer control regi ster (wdtctl) to configure the wdt and its oscillator to be disabled duri ng stop mode. alte rnatively, write 00h to the wdtctl as the third step in this sequence to reconfigure the wdt and its oscillator to be enabled during stop mode. this se quence only affects wdt operation in stop mode.
ps022517-0508 watchdog timer z8 encore! xp ? f0822 series product specification 85 wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the wdt forces the device into the reset state. the wdt status bit in the wdt control regi ster is set to 1. for more infor- mation on reset, see reset and stop mode recovery on page 39. wdt reset in stop mode if enabled in stop mode and configured to generate a reset when a time-out occurs and the device is in stop mode, the wdt initiates a stop mode recove ry. both the wdt status bit and the stop bit in the wdt control regi ster is set to 1 following wdt time-out in stop mode. fo r more information on reset, see reset and stop mode recovery on page 39. default operation is for th e wdt and its rc oscillator to be enabled during stop mode. wdt rc disable in stop mode to minimize power consumption in stop mo de, the wdt and its rc oscillator can be disabled in stop mode. the following sequence configures the wdt to be disabled when the z8f082x family devi ce enters stop mode following execution of a stop instruction: 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write 81h to the watchdog timer control regi ster (wdtctl) to configure the wdt and its oscillator to be disabled duri ng stop mode. alte rnatively, write 00h to the watchdog timer control register (wdtctl) as the third step in this sequence to reconfigure the wdt and its oscillator to be enabled during stop mode. this sequence only affects wdt operation in stop mode. watchdog timer relo ad unlock sequence writing the unlock sequence to the wdtctl address unlocks the three watchdog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time-out period. these write operations to the wdtctl address produce no effect on the bits in the wdtctl. the locking mechanism prevents spurious writes to the reload registers. the following sequence is requir ed to unlock the watchdog timer reload byte registers (wdtu, wdth, and wd tl) for write access. 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu). 4. write the watchdog timer reload high byte register (wdth). 5. write the watchdog timer relo ad low byte register (wdtl).
ps022517-0508 watchdog timer z8 encore! xp ? f0822 series product specification 86 all three watchdog timer reload registers must be written in this order. there must be no other register writes between each of thes e operations. if a register write occurs, the lock state machine resets and no further writes occur unless the seque nce is restarted. the value in the watchdog timer reload registers is loaded into the counter when the wdt is first enabled and every time a wdt instruction is executed. watchdog timer control register definitions watchdog timer control register the watchdog timer control re gister (wdtctl), detailed in table 48 , is a read-only register that indicates the source of the most recent reset event, a stop mode recovery event, and a wdt time-out. reading this re gister resets the upper four bits to 0. writing the 55h , aah unlock sequence to the watc hdog timer control register (wdtctl) address unlocks the three watch dog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the ti me-out period. these write operations to the wdtctl address produce no effect on the bits in the wdtctl. the locking mechanism prevents spurious writes to the reload registers. por?power-on reset indicator if this bit is set to 1, a por event occurred. this bit is reset to 0, if a wdt time-out or stop mode recovery occurs. this bit is also reset to 0, when the register is read. table 48. watchdog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset see descriptions below 0 r/w r addr ff0h reset or stop mode recovery event por stop wdt ext power-on reset 1000 reset through reset pin assertion 0001 reset through wdt time-out 0010 reset through the ocd (octctl[1] set to 1) 1000 reset from stop mode through the dbg pin driven low1000 stop mode recovery through gpio pin transition 0100 stop mode recovery through wdt time-out 0110
ps022517-0508 watchdog timer z8 encore! xp ? f0822 series product specification 87 stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurred. if the stop and wdt bits are both set to 1, the stop mode recovery occurred due to a wd t time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a por or a wdt time-out that o ccurred while not in stop mode. reading this register also resets this bit. wdt?watchdog timer time-out indicator if this bit is set to 1, a wdt time-out occu rred. a por resets this pin. a stop mode recovery due a change in an input pin also r esets this bit. reading this register resets this bit. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a por or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. reserved these bits are reserved and must be 0. watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, hi gh and low byte (wdtu, wdth, wdtl) registers ( table 49 through table 51 ) form the 24-bit re load value that is loaded into the wdt, when a wdt instruction executes. the 24-bit reload value is {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writing to these regi sters sets the required reload value. reading from these registers retu rns the current wdt count value. the 24-bit wdt reload value must not be set to a value less than 000004h . wdtu?wdt reload upper byte most significant byte (msb), bits[23: 16], of the 24-bit wdt reload value. table 49. watchdog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset 1 r/w r/w* addr ff1h r/w*?read returns the current wdt count value. write sets the desired reload value. caution:
ps022517-0508 watchdog timer z8 encore! xp ? f0822 series product specification 88 wdth?wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 24-bit wdt reload value. table 50. watchdog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 1 r/w r/w* addr ff2h r/w*?read returns the current wdt count value. write sets the desired reload value. table 51. watchdog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 1 r/w r/w* addr ff3h r/w*?read returns the current wdt count value. write sets the desired reload value.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 89 universal asynchronous receiver/transmitter the universal asynchronous receiver/transmitter (u art) is a full-duplex communication channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectabl e parity. features of the uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun, and break detection ? separate transmit and receive enables ? 16-bit baud rate generator ? selectable multiprocessor (9-bit) mode w ith three configurable interrupt schemes ? brg timer mode ? driver enable output for external bus transceivers architecture the uart consists of three primary functional blocks: tran smitter, receiver, and baud rate generator. the uart?s transmitter and receiver functions in dependently, but use the same baud rate and data format. figure11 on page 90 displays the uart architecture.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 90 figure 11. uart block diagram operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit is optiona lly added to the data stream. each character begins with an active low start bit and ends with eith er 1 or 2 active high stop bits. figure12 on page 91 and figure13 on page 91 display the as ynchronous data format used by the uart without parity and with parity, respectively. receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 91 figure 12. uart asynchronous data format without parity figure 13. uart asynchronous da ta format with parity transmitting data using polled method follow the steps below to transmit data using polled method of operation: 1. write to the uart baud rate high byte and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. if multiprocessor mode is required, writ e to the uart control 1 register to enable multiprocessor (9 -bit) mode functions. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 4. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? if parity is required, and multiprocessor mode is not enabled, set the parity enable bit ( pen ) and select either even or odd parity ( psel ). ? set or clear the ctse bit to enable or disable co ntrol from the remote receiver using the cts pin. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 92 5. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 6 . if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register becomes ava ilable to receive new data. 6. write the uart control 1 register to select the outgoing address bit: ? set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 7. write data byte to the uart transmit da ta register. the transmitter automatically transfers data to the transmit shift re gister and then transmits the data. 8. if required, and multiprocessor mode is enabled, make any changes to the multiprocessor bit transmitter ( mpbt ) value. 9. to transmit additional bytes, return to step 5 . transmitting data using interrupt-driven method the uart transmitter interrupt indicates the ava ilability of the transmit data register to accept new data for transmission. follow th e below steps to configure the uart for interrupt-driven data transmission: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the required priority. 5. if multiprocessor mode is required, wr ite to the uart control 1 register to enable multiprocessor (9 -bit) mode functions: ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 6. write to the uart control 0 register to: ? set the transmit enable ( ten ) bit to enable the uart for data transmission ? enable parity, if required, and if mu ltiprocessor mode is not enabled, and select either even or odd parity. ? set or clear the ctse bit to enable or disable co ntrol from the remote receiver through the cts pin. 7. execute an ei instruction to enable interrupts.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 93 the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interru pt is generated immediately. when the uart transmit interrupt is detected, the as sociated isr performs the following: 1. write the uart control 1 register to select the outgoing address bit: ? set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 2. write the data byte to the uart tr ansmit data register. the transmitter automatically transfers data to the transmit shift register and then transmits the data. 3. clear the uart transmit interrupt bit in th e applicable interrupt request register. 4. execute the iret instruction to return from the isr and waits for the transmit data register to again become empty. receiving data using the polled method follow the steps below to configur e the uart for polled data reception: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiprocessor mode functions, if desired. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if required, and if mu ltiprocessor mode is not enabled, and select either even or odd parity. 5. check the rda bit in the uart status 0 register to determine if the receive data register contains a valid data byte (indicated by 1). if rda is set to 1 to indicate available data, continue to step 6 . if the receive data register is empty (indicated by a 0), continue to monito r the rda bit awaiting reception of the valid data. 6. read data from the uart receive data register. if operating in multiprocessor (9-bit) mode, further actions may be requir ed depending on the multiprocessor mode bits mpmd[1:0]. 7. return to step 5 to receive additional data.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 94 receiving data using in terrupt-driven method the uart receiver interrupt indicates the av ailability of new data (as well as error con- ditions). follow the steps belo w to configure the uart receive r for interrupt-driven oper- ation: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the required priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if desired. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. ? set the multiprocessor mode bits, mpmd[1:0] , to select the required address matching scheme. ? configure the uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for z8 encore! xp devices without a dma block) 7. write the device address to the address compare register (aut omatic multiprocessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if required, and if mu ltiprocessor mode is not enabled, and select either even or odd parity. 9. execute an ei instruction to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associated isr performs the following: 1. check the uart status 0 register to dete rmine the source of the interrupt-error, break, or received data. 2. if the interrupt was due to data available, read the data from the uart receive data register. if operating in multiprocessor (9-bit) mode, furthe r actions may be required depending on the multip rocessor mode bits mpmd[1:0]. 3. clear the uart receiver interrupt in th e applicable interrupt request register. 4. execute the iret instruction to return from the isr and await more data.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 95 clear to send operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transm it datastream. the clear to send (cts ) input pin is sampled one system clock before beginning any new character transmission. to delay transmission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transmission begins. for multiple character transmissions, this would be done during stop bit transmission. if cts deasserts in the middle of a character tr ansmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common uart bus. in multiprocessor mode (also referred to as 9-bit mode), the multiprocessor bit is transmitted following the 8-bits of data and immediately preceding the stop bit(s) as dis- played in figure 14 . the character format is as displayed in figure 14 . figure 14. uart asynchronous multiprocessor mode data format in multiprocessor (9-bit) mode, the pari ty bit location (9th bit) becomes the multiprocessor control bit. the uart control 1 and st atus 1 registers provide multiprocessor (9-bit) mode control and status information. if an automatic address matching scheme is enable d, the uart address compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only proc esses frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software, or combin ation of the two depending on the multiprocessor configura- tion bits. in general, the address compare feat ure reduces the load on the cpu, because it does not need to access the uart when it receives data directed to other devices on the start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 96 multi-node network. the following multip rocessor modes are available in hard- ware: ? interrupt on all address bytes. ? interrupt on matched address bytes and correctly framed data bytes. ? interrupt only on corre ctly framed data bytes. these modes are selected with mpmd[1:0] in the uart control 1 register. for all multiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0] . in this mode, all incoming address bytes cause an interrupt, while da ta bytes never cause an interrupt. the isr must manually check the address byte th at caused triggered the interrupt. if it matches the uart address, the software should clear mpmd[0] . at this point, each new incoming byte interrupts the cp u. the software is then re sponsible for determining the end-of-frame. it checks for the end-of-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx=1 , then a new frame begins. if the address of this new frame is different from the uart?s address, then mpmd[0] must be set to 1 causing the uart interru pts to go inactive until the ne xt address byte. if the new frame?s address matches the uart?s address, then the data in the new frame should be processed as well. the second scheme is enabled by setting mpmd[1:0] to 10b and writing the uart?s address into the uart address co mpare register. this mode introduces more hardware control, interrupting only on frames that match the uart?s address. when an incoming address byte does not match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte oc curs, an interrupt is issued and further interrupts occur on each successive data byte. the first data byte in the frame contains the newfrm =1 in the uart status 1 register. when the next address byte occurs, the hardware compares it to the uart? s address. if there is a match, the interrupts continue and the newfrm bit is set for the first byte of the new frame. if ther e is no match, then the uart ignores all incoming bytes until the next address match. the third scheme is enabled by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame is still accompanied by a newfrm assertion. external driver enable the uart provides a driver enable (de) signal for off-chip bus transceivers. this feature reduces the software overhead associat ed with using a gpio pin to control the transceiver when communicating on a mu lti-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as displayed in figure15 on page 97. the driver enable signal asserts when a byte is written to the uart transmit data register. the driver
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 97 enable signal asserts at least one uart bit pe riod and no greater than two uart bit peri- ods before the start bit is tran smitted. this format allows a se tup time to enable the trans- ceiver. the driver enable signal deasserts one system clock period after the last stop bit is transmitted. this one system clock delay allows both time for data to clear the trans- ceiver before disabling it, as we ll as the ability to determine if another character follows the current character. in the even t of back to back characters (new data must be written to the transmit data register before the previous character is completely transmitted) the de signal is not deasserted between char acters. the depol bit in the uart control register 1 sets the polarity of the driver enable signal. figure 15. uart driver enable signal timing (with 1 stop bit and parity) the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary function ality is disabled, the brg also functions as a basic timer with interrupt capability. transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the transmitter is ready to accept new data for transmission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. at this point, the tran smit data register can be written with the next character to send. this provides 7 bit periods of latency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ---------------------------------------- - ? ? ? ? de to start bit setup time (s) 2 baud rate (hz) ---------------------------------------- - ?? ?? ?
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 98 receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte is received and is available in the uart receive data register. this interrupt can be disabled independent of the other receiver interrupt sources. the received data interrupt occurs once the rece ive character is received and placed in the receive data register. software must re spond to this received data available condition before the next charact er is completely received to avoid an overrun error. in multiprocessor mode ( mpen = 1), the receive data interrupts are dependent on the multiprocessor configuration an d the most rece nt address byte ? a break is received ? an overrun is detected ? a data framing error is detected uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until the valid data is read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break de tect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte cannot contain va lid data and should be ignored. the brkd bit indi- cates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun error, the receive data register must be read again to clear the error bits is the uart status 0 register. upda tes to the receive data register occur only when the next data word is received. uart data and error handling procedure figure16 on page 99 displays the recommen ded procedure for uart receiver isrs. baud rate generator interrupts if the brg interrupt enable is set, the uar t receiver interrupt asserts when the uart baud rate generator reloads. this action allows the brg to function as an additional counter if the uart functi onality is not employed.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 99 figure 16. uart receiver interrupt service routine flow uart baud rate generator the uart baud rate generator creates a lo wer frequency baud rate clock for data transmission. the input to the brg is the sy stem clock. the uart baud rate high and low byte registers combine to create a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated using the following equation: receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data uart data rate (bits/s) system clock frequency (hz) 16xuart baud rate divisor value --------------------------------------------------------------------------------------------- =
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 100 when the uart is disabled, the brg functions as a basic 16-bit timer with interrupt on time-out. follow the steps below to configure the brg as a timer with interrupt on time- out: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the desired 16-bit co unt value into the uart baud rate high and low byte registers. 3. enable the brg timer function and associated interrupt by setting the bkgctl bit in the uart control 1 register to 1. when configured as a general-purpose timer, th e interrupt interval is calculated using the following equation: interrupt interval (s) = system clock period (s) brg[15:0] ] uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. see infrared encoder/decoder on page 109 for more in formation on the infra- red operation. uart transmit data register data bytes written to the uar t transmit data register ( table 52 ) are shifted out on the txd x pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. table 52. uart transmit data register (u0txd) bits 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww addr f40h
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 101 uart receive data register data bytes received through the rxd x pin are stored in the uart receive data register ( table 53 ). the read-only uart receive data register shares a register file address with the write-only uart transmit data register. rxd?receive data uart receiver data byte from the rxd x pin uart status 0 register the uart status 0 and status 1 registers ( table 54 and table 55 on page 102) identify the current uart operating configuration and status. rda?receive data available this bit indicates that the uart receive da ta register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. pe?parity error this bit indicates that a parity error has occurred. reading the uart receive data regis- ter clears this bit. 0 = no parity error has occurred. 1 = a parity error has occurred. oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to table 53. uart receive data register (u0rxd) bits 7 6 5 4 3 2 1 0 field rxd reset x r/w r addr f40h table 54. uart status 0 register (u0stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 01x r/w r addr f41h
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 102 0, then reading the uart receive da ta register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (n o stop bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multiprocessor bit, and stop bit(s) are all zeros then this bit is se t to 1. reading the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is read y to receive an additional byte to be transmitted. txe?transmitter empty this bit indicates that the transmit shift register is empty and character transmission is finished. 0 = data is currently transmitting. 1 = transmission is complete. cts?cts signal when this bit is read it re turns the level of the cts signal. uart status 1 register this register contains multiprocessor control and status bits. table 55. uart status 1 register (u0stat1) bits 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 0 r/w rr/wr addr f44h
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 103 reserved?must be 0 newfrm? status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the fi rst data byte of a new frame. mprx?multiprocessor receive returns the value of the last multiprocessor bit received. re ading from the uart receive data register resets this bit to 0. uart control 0 and c ontrol 1 registers the uart control 0 and control 1 registers ( table 56 and table 57 on page 104) config- ure the properties of the uart?s transmit and receive operations. the uart control registers must not been written while the uart is enabled. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. this bit is overridden by the mpen bit. 0 = parity is disabled. 1 = the transmitter sends data with an additional parity bit and the receiver receives an additional parity bit. table 56. uart control 0 register (u0ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 0 r/w r/w addr f42h
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 104 psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted an d expected on all received data. sbrk?send break this bit pauses or breaks data transmission by forcing the transmit data output to 0. sending a break interrupts any tr ansmission in progress, so en sure that the transmitter has finished sending data before setting this bit. the uart does not automatically generate a stop bit when sbrk is deasserted. software must time the duration of the break and the duration of any stop bit time desired following the break. 0 = no break is sent. 1 = the output of the transmitter is zero. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver. mpmd[1:0]?multiprocessor mode if multiprocessor (9-bit) mode is enabled, 00 = the uart generates an interrupt requ est on all received bytes (data and address). 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt requ est when a received address byte matches the value stored in the addres s compare register and on all successive data bytes until an address mismatch occurs. 11 = the uart generates an interrupt requ est on all received data bytes for which the most recent address byte ma tched the value in the address compare register. mpen?multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiproces sor (9-bit) mode. table 57. uart control 1 register (u0ctl1) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 0 r/w r/w addr f43h
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 105 mpbt?multiprocessor bit transmit this bit is applicable only when mu ltiprocessor (9-bit) mode is enabled. 0 = send a 0 in the multipro cessor bit location of the data stream (9th bit). 1 = send a 1 in the multipro cessor bit location of the data stream (9th bit). depol?driver enable polarity 0 = de signal is active high. 1 = de signal is active low. brgctl?baud rate control this bit causes different uart behavior de pending on whether the uart receiver is enabled (ren = 1 in the uart control 0 register). when the uart receiver is not enabled, this bit determin es whether the brg will issue interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value 1 = the brg generates a receive interrupt when it counts down to zero. reads from the baud rate hi gh and low byte registers return the current brg count value. when the uart receiver is enab led, this bit allows reads from the baud rate registers to return the brg count value in stead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and lo w byte registers return the current brg count value. unlik e the timers, there is no mech anism to latch the high byte when the low byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors ge nerates an interrupt request to the interrupt controller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is disabled . uart operates normally operation. 1 = infrared encoder/decoder is enabled. the uart transmits and receives data through the infrared encoder/decoder. uart address compare register the uart address compare register stores th e multi-node network address of the uart. when the mpmd[1] bit of uart control regi ster 0 is set, all incoming address bytes will be compared to the value stored in the address compare register. receive interrupts and rda assertions will only occur in the event of a match.
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 106 comp_addr?compare address this 8-bit value is compared to the incoming address bytes. uart baud rate high and low byte registers the uart baud rate high and low byte registers ( table 59 and table 60 ) combine to create a 16-bit baud rate divisor value (brg[1 5:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calcula ted using the following equation: table 58. uart address compare register (u0addr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 0 r/w r/w addr f45h table 59. uart baud rate high byte register (u0brh) bits 7 6 5 4 3 2 1 0 field brh reset 1 r/w r/w addr f46h table 60. uart baud rate low byte register (u0brl) bits 7 6 5 4 3 2 1 0 field brl reset 1 r/w r/w addr f47h uart baud rate (bits/s) system clock frequency (hz) 16 xuart baud ra te divisor value ---------------------------------------------------------------------------------------------- - =
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 107 for a given uart data rate, the integer baud rate divisor value is calculated using the following equation: the baud rate error relative to the desired baud rate is calculat ed using the following equation: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 61 provides information on data rate erro rs for popular baud rates and commonly used crystal osc illator frequencies. table 61. uart baud rates 10.0 mhz system clock 5.5296 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 -16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 -1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 -0.03 2.40 144 2.40 0.00 1.20 521 1.20 -0.03 1.20 288 1.20 0.00 0.60 1042 0.60 -0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.2 0.30 1152 0.30 0.00 uart baud rate divisor value (brg) round system clock frequency (hz) 16xuart data rate (bits/s) ------------------------------------------------------------------------------- ?? ?? = uart baud rate error (%) 100x actual data rate desired data rate ? desired data rate ---------------------------------------------------------------------------------------------------- ?? ?? =
ps022517-0508 universal asynchronous receiver/transmitter z8 encore! xp ? f0822 series product specification 108 3.579545 mhz system clock 1.8432 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 -10.51 250.0 n/a n/a n/a 115.2 2 111.9 -2.90 115.2 1 115.2 0.00 57.6 4 55.9 -2.90 57.6 2 57.6 0.00 38.4 6 37.3 -2.90 38.4 3 38.4 0.00 19.2 12 18.6 -2.90 19.2 6 19.2 0.00 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 -0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 -0.04 0.60 192 0.60 0.00 0.30 746 0.30 -0.04 0.30 384 0.30 0.00 table 61. uart baud rates (continued)
ps022517-0508 infrared encoder/decoder z8 encore! xp ? f0822 series product specification 109 infrared encoder/decoder z8 encore! xp ? f0822 series products contain a fully-functional, high-performance uart to infrared encoder/decode r (endec). the infrared endec is integrated with an on- chip uart to allow easy comm unication between the z8 encore! xp and irda physical layer specification, v1.3-compliant infrare d transceivers. infrare d communication pro- vides secure, reliable, low-co st, point-to-point communica tion between pcs, pdas, cell phones, printers, and other infrared enabled devices. architecture figure 17 displays the architecture of the infrared endec. figure 17. infrared data communication system block diagram operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infrared transceiver through th e txd pin. similarly, data received from the infrared transceiver is passed to the infrared endec th rough the rxd pin, decoded by the infrared endec, and then passed to the uart. communication is half-duplex, which means simultaneous data transmission and reception is not allowed. interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data zilog rxd txd baud rate clock (endec) zhx1810 infrared transceiver
ps022517-0508 infrared encoder/decoder z8 encore! xp ? f0822 series product specification 110 the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enable d to use the infrared endec. the infrared endec data rate is calculated using the following equation. transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16-clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16-clock period. if the data to be transmi tted is 0, a 3-clock high pulse is output following a 7-clock low period. after the 3-clock high pulse, a 6-clock low pulse is output to complete the fu ll 16-clock data period. figure 18 displays irda data transmis- sion. when the infrared endec is enabled, th e uart?s txd signal is internal to the z8 encore! xp ? f0822 series products while the ir_txd signal is output through the txd pin. figure 18. infrared data transmission infrared data rate (bits/s) system clock frequency (hz) 16xuart baud rate divisor value --------------------------------------------------------------------------------------------- = baud rate ir_txd uart?s 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3-clock pulse txd clock
ps022517-0508 infrared encoder/decoder z8 encore! xp ? f0822 series product specification 111 receiving irda data data received from the infrared transceiver through the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to genera te the demodulated signa l (rxd) that drives the uart. each uart/infrared da ta bit is 16-clocks wide. figure 19 displays data recep- tion. when the infrared endec is enabled, the uart?s rxd sign al is internal to the z8 encore! xp ? f0822 series products while the ir_rxd signal is received through the rxd pin. figure 19. infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper reception of the 1.6 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the window remains open until the count again reaches 8 (or in other words 24 baud clock periods since the previous pulse was detected ). this gives the endec a sampling window baud rate uart?s ir_rxd 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8-clock delay clock rxd 16-clock period 16-clock period 16-clock period 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.6 s pulse caution:
ps022517-0508 infrared encoder/decoder z8 encore! xp ? f0822 series product specification 112 of minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. if an incoming pulse is de tected inside this window this process is repeated. if the incoming data is a logical 1 (n o pulse), the endec returns to the initial state and waits for the next falling edge. as eac h falling edge is detected, the endec clock counter is reset, resynchronizing the endec to the incoming signal. this procedure allows the endec to tolerate jitter and baud rate errors in the incoming data stream. resynchroniz- ing the endec does not alter the operation of the uart, which ultimately receives the data. the uart is only synchronized to the incoming data stream when a start bit is received. infrared endec control register definitions all infrared endec configuration and status information is set by the uart control registers as defined in uart control register definitions on page 100. to prevent spurious signals during irda data transmission, set the iren bit in the uart control 1 register to 1 to enable th e infrared endec befo re enabling the gpio port alternate function for the corresponding pin. caution:
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 113 serial peripheral interface the serial peripheral interface (spi) is a synchronous interf ace allowing several spi-type devices to be interconne cted. spi-compatible devices include eeproms, analog-to- digital converters, and isdn devices. features of the spi include: ? full-duplex, synchronous, and character-oriented communication ? four-wire interface ? data transfers rates up to a maximum of one-half the system clock frequency ? error detection ? dedicated baud rate generator the spi is not available in 20-pin package devices. architecture the spi is be configured as e ither a master (in single or multi-master systems) or a slave as displayed in figure 20 through figure 22 . figure 20. spi configured as a master in a single master, single slave system spi master 8-bit shift register bit 0 bit 7 miso mosi sck ss to slave?s ss pin from slave to slave to slave baud rate generator
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 114 figure 21. spi configured as a master in a single master, multiple slave system figure 22. spi configured as a slave operation the spi is a full-duplex, synchronous, and char acter-oriented channel that supports a four- wire interface (serial clock, transmit, receive and slave select). the spi block consists of a transmit/receive shift regist er, a baud rate (clock) ge nerator and a control unit. spi master 8-bit shift register bit 0 bit 7 miso mosi sck gpio to slave #2?s ss pin from slave to slave to slave ss baud rate generator vcc gpio to slave #1?s ss pin spi slave 8-bit shift register bit 7 bit 0 miso mosi sck ss from master to master from master from master
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 115 during an spi transfer, data is sent and recei ved simultaneously by both the master and the slave spi devices. separate signals are requ ired for data and the serial clock. when an spi transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneou sly shifted in on a second data pin. an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular buffer. the spi shift register is single-buffered in th e transmit and receive directions. new data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read. spi signals the four basic spi signals are: ? miso (master-in, slave-out) ? mosi (master-out, slave-in) ? sck (serial clock) ? ss (slave select) the following sections discuss these spi signals. each signal is described in both master and slave modes. master-in/slave-out the master-in/slave-out (miso) pin is configur ed as an input in a master device and as an output in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. the miso pin of a slave device is placed in a high-impedance state if the slave is not selected. when the sp i is not enabled, this signal is in a high- impedance state. master-out/slave-in the master-out/slave-in (mosi) pin is configured as an output in a master device and as an input in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. when the spi is not enabled, this signal is in a high-impedance state. serial clock the serial clock (sck) synchronizes data movement both in and out of the device through its mosi and miso pins. in mas ter mode, the spi?s baud rate generator creates the serial clock. the master drives the serial clock out its own sck pin to the slave?s sck pin. when the spi is configured as a slave, the sck pin is an input and the clock signal from the master synchronizes th e data transfer between the master and slave devices. slave devices ignore the sck signal, unless the ss pin is asserted. when config- ured as a slave, the spi block requires a minimu m sck period of greater than or equal to 8 times the system (xin) clock period.
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 116 the master and slave are each capable of exchanging a character of data during a sequence of numbits clock cycles (see numbit s field in the spimode register). in both master and slave spi devices, data is sh ifted on one edge of the sck and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi phase and polarity control. slave select the active low slave select (ss ) input signal selects a slave spi device. ss must be low prior to all data communication to and from the slave device. ss must stay low for the full duration of each character transferred. the ss signal can stay low during the transfer of multiple characters or can de assert between each character. when the spi is configured as the only master in an spi system, the ss pin is set as either an input or an output. for communication betwee n the z8 encore! xp f0822 series device?s spi master and external slave devices, the ss signal, as an output, asserts the ss input pin on one of the slave devices. other gpio output pins can also be employed to select external spi slave devices. when the spi is configured as one master in a multi-master spi system, the ss pin should be set as an input. the ss input signal on the master must be high. if the ss signal goes low (indicating another master is driving the spi bus), a collision error flag is set in the spi status register. spi clock phase and polarity control the spi supports four combinations of serial cl ock phase and polarity using two bits in the spi control register. the clock polarity bit, clkpol , selects an active high or active low clock and has no effect on the transfer format. table 62 lists the spi clock phase and polarity operation parameters. the clock phase bit, phase , selects one of two fundamen- tally different transfer formats. for proper da ta transmission, the clock phase and polarity must be identical for the spi master and the spi slave. the master always places data on the mosi line a half-cycle befo re the receive clock edge (sck signal), in order for the slave to latch the data. table 62. spi clock phase (phase) and clock polarity (clkpol) operation phase clkpol sck transmit edge sck receive edge sck idle state 0 0 falling rising low 0 1 rising falling high 1 0 rising falling low 1 1 falling rising high
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 117 transfer format phase is 0 figure 23 displays the timing diagram for an spi transfer in which phase is cleared to 0. the two sck waveforms show polarity with clkpol reset to 0 and with clkpol set to one. the diagram can be interpreted as either a master or slave timing diagram since the sck master-in/slave-out (m iso) and master-out/slave-in (mosi) pins are directly connected between the master and the slave. figure 23. spi timing when phase is 0 transfer format phase is 1 figure 24 displays the timing diagram for an spi transfer in which phase is one. two waveforms are depicted for sck, one for cl kpol reset to 0 and another for clkpol set to 1. sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 118 figure 24. spi timing when phase is 1 multi-master operation in a multi-master spi system, all sck pins are tied together, all mosi pins are tied together and all miso pins are tied together. all spi pins must then be configured in open-drain mode to prevent bus contention . at any one time, only one spi device is configured as the master and all other spi de vices on the bus are configured as slaves. the master enables a single slave by asserting the ss pin on that slave only. then, the single master drives data out its sck and mo si pins to the sck and mosi pins on the slaves (including those which are not enable d). the enabled slave drives data out its miso pin to the miso master pin. for a master device operating in a multi-master system, if the ss pin is configured as an input and is driven lo w by another master, the col bit is set to 1 in the spi status register. the col bit indicates the occurrence of a multi-master collision (mode fault error condition). slave operation the spi block is configured for slave mode operation by setting the spien bit to 1 and the mmen bit to 0 in the sp ictl register and setting the ssio bit to 0 in the spimode register. the irqe, phase, clkpol, and wor bits in the spictl register and the sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 119 numbits field in the spimode register must be set to be consistent with the other spi devices. the str bit in the spictl register can be used if desired to force a ?startup? interrupt. the birq bit in the spictl register and the ssv bit in the spimode register is not used in slave mode . the spi baud rate ge nerator is not used in slave mode so the spibrh and spibrl registers need not be initialized. if the slave has data to send to the mast er, the data must be written to the spidat register before the transaction starts (first edge of sck when ss is asserted). if the spidat register is not written prior to th e slave transaction, the miso pin outputs whatever value is currently in the spidat register. due to the delay resulting from synchronization of the spi input signals to the internal system clock, the maximum spiclk baud rate that can be supported in slave mode is the system clock frequency (xin) divided by 8. this rate is controlled by the spi master. error detection the spi contains error detection logic to support spi communication protocols and recog- nize when communication errors have occurred. the spi status register indicates when a data transmission error has been detected. overrun (write collision) an overrun error (write collision) indicates a write to the spi data register was attempted while a data transfer is in pr ogress (in either master or slave modes). an overrun sets the ovr bit in the spi status register to 1. writi ng a 1 to ovr clears this error flag. the data register is not altered when a write occu rs while data transfer is in progress. mode fault (multi-master collision) a mode fault indicates when mo re than one master is trying to communicate at the same time (a multi-master collision). the mode fault is detected when the enabled master?s ss pin is asserted. a mode fault sets the col bit in the spi status register to 1. writing a 1 to col clears this error flag. slave mode abort in slave mode, if the ss pin deasserts before all bits in a character have been transferred, the transaction aborts . when this condition occurs the abt bit is set in the spistat register as well as the irq bit (indicating the transaction is complete). the next time ss asserts, the miso pin outputs spidat[ 7], regardless of where the previous transaction left off. writing a 1 to abt clears this error flag. spi interrupts when spi interrupts are enabled, the spi gene rates an interrupt after character transmis- sion/reception completes in both master and sl ave modes. a character is defined to be 1 through 8 bits by the numbits field in the spi mode regist er. in slave mode it is not
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 120 necessary for ss to deassert between characters to generate the interrupt. the spi in slave mode also generates an interrupt if the ss signal deasserts prior to transfer of all the bits in a character (see description of slave abort error). writing a 1 to the irq bit in the spi status register clears the pending spi interrupt request. the irq bit must be cleared to 0 by the isr to generate future inte rrupts. to start the transfer process, an spi interrupt can be forced by so ftware writing a 1 to the str bit in the spictl register. if the spi is disabled, an spi interrupt can be generated by a brg time-out. this timer function must be enabled by setting the birq bit in th e spictl register. this brg time-out does not set the irq bit in the spistat register, just the sp i interrupt bit in the interrupt controller. spi baud rate generator in spi master mode, the brg creates a lo wer frequency serial clock (sck) for data transmission synchronization between the master and the external slave. the input to the brg is the system clock. the spi baud rate high and low byte registers combine to form a 16-bit reload value, br g[15:0], for the spi baud ra te generator. the spi baud rate is calculated usin g the following equation: minimum baud rate is obtained by setting brg [15:0] to 0000h for a clock divisor value of (2 x 65536 = 131072). when the spi is disabled, brg functions as a basic 16-bit timer with interrupt on time-out. follow the steps below to configure brg as a timer with interrupt on time-out: 1. disable the spi by clearing the spien bit in the spi control register to 0. 2. load the desired 16-bit co unt value into the spi baud rate high and low byte registers. 3. enable brg timer function and as sociated interrupt by setting the birq bit in the spi control register to 1. when configured as a general-purpose timer, th e interrupt interval is calculated using the following equation: interrupt interval (s) = system clock period (s) brg[15:0] ] spi baud rate (bits/s) system clock frequency (hz) 2xbrg[15:0] ------------------------------------------------------------------------------- =
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 121 spi control register definitions spi data register the spi data register stores both the outgoing (transmit) data and th e incoming (receive) data. reads from the spi data register always return the current contents of the 8-bit shift register. data is shifted out starting with bit 7. the last bit received resides in bit position 0. with the spi configured as a master, writing a da ta byte to this register initiates the data transmission. with the spi conf igured as a slave, writing a data byte to this register loads the shift register in preparation for the next data transfer with the external master. in either the master or slave modes, if a transmission is already in progress, writes to this register are ignored and the overrun error flag, ovr , is set in the spi status register. when the character length is le ss than 8 bits (as set by the numbits field in the spi mode register), the transmit character must be left justified in the spi data register. a received character of less than 8 bits is right justifie d (last bit received is in bit position 0). for example, if the spi is configured for 4-bi t characters, the transmit characters must be written to spidata[7:4] and the received characters are read from spidata[3:0]. data?data transmit and/or receive data. table 63. spi data register (spidata) bits 7 6 5 4 3 2 1 0 field data reset x r/w r/w addr f60h
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 122 spi control register the spi control register configures the spi for transmit and receive operations. irqe?interrupt request enable 0 = spi interrupts are disabled. no interrupt requests are sent to the interrupt controller. 1 = spi interrupts are enabled. interrupt re quests are sent to the interrupt controller. str?start an spi interrupt request 0 = no effect. 1 = setting this bit to 1 also sets the irq bit in the spi status register to 1. setting this bit forces the spi to send an interrupt request to the interrupt control. this bit can be used by software for a functio n similar to transmit buffer empty in a uart. writing a 1 to the irq bit in the spi status register clears this bit to 0. birq?brg timer interrupt request if the spi is enabled, this bit h as no effect. if the spi is disabled: 0 = brg timer function is disabled. 1 = brg timer function and tim e-out interrupt are enabled. phase?phase select sets the phase relationship of the data to the clock. for more information on operation of the phase bit, see spi clock phase and polarity control on page 116. clkpol?clock polarity 0 = sck idles low (0). 1 = sck idle high (1). wor?wire-or (open-drain) mode enabled 0 = spi signal pins not configured for open-drain. 1 = all four spi signal pins (sck, ss , miso, mosi) configured for open-drain function. this setting is typically used for multi- master and/or multi-sl ave configurations. mmen?spi master mode enable 0 = spi configured in slave mode. 1 = spi configured in master mode. spien?spi enable 0 = spi disabled. 1 = spi enabled. table 64. spi control register (spictl) bits 7 6 5 4 3 2 1 0 field irqe str birq phase clkpol wor mmen spien reset 0 r/w r/w addr f61h
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 123 spi status register the spi status register indicates the current st ate of the spi. all bits revert to their reset state if the spien bit in the spictl register equals 0. irq?interrupt request if spien = 1, this bit is set if the str bit in the spictl register is set, or upon comple- tion of an spi master or slave transaction. th is bit does not set if spien = 0 and the spi baud rate generator is used as a tim er to generate the spi interrupt. 0 = no spi interrupt request pending. 1 = spi interrupt request is pending. ovr?overrun 0 = an overrun error has not occurred. 1 = an overrun error has been detected. col?collision 0 = a multi-master collision (m ode fault) has not occurred. 1 = a multi-master collision (mod e fault) has been detected. abt?slave mode transaction abort this bit is set if the spi is configured in slave mode, a transaction is occurring and ss deasserts before all bits of a character have been transferred as defined by the numbits field of the spimode register. the irq bi t also sets, indicating the transaction has completed. 0 = a slave mode transaction abort has not occurred. 1 = a slave mode transaction abort has been detected. reserved?must be 0 txst?transmit status 0 = no data transmission currently in progress. 1 = data transmission cu rrently in progress. slas?slave select if spi enabled as a slave 0 = ss input pin is asserted (low) 1 = ss input is not asserted (high). if spi enabled as a master, th is bit is not applicable. table 65. spi status register (spistat) bits 7 6 5 4 3 2 1 0 field irq ovr col abt reserved txst slas reset 01 r/w r/w* r addr f62h r/w* = read access. write a 1 to clear the bit to 0.
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 124 spi mode register the spi mode register configures the charac ter bit width and the direction and value of the ss pin. reserved?must be 0 diag?diagnostic mode control bit this bit is for spi diagnostics. setting this bit allows the brg value to be read using the spibrh and spibrl register locations. 0 = reading spibrh, spibrl returns the valu e in the spibrh and spibrl registers 1 = reading spibrh returns bits [15:8] of the spi baud rate generator; and reading spibrl returns bits [7:0] of the spi baud rate counter. the baud rate counter high and low byte values are not buffered. take precautions if you are readin g the values while brg is counting. numbits[2:0]?number of data bi ts per character to transfer this field contains the number of bits to sh ift for each character transfer. see the spi data register description for information on valid b it positions when the char acter length is less than 8-bits. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits 110 = 6 bits 111 = 7 bits ssio?slave select i/o 0 = ss pin configured as an input. 1 = ss pin configured as an output (master mode only). ssv?slave select value if ssio = 1 and spi configured as a master: 0 = ss pin driven low (0). table 66. spi mode register (spimode) bits 7 6 5 4 3 2 1 0 field reserved diag numbits[2:0] ssio ssv reset 0 r/w rr/w addr f63h caution:
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 125 1 = ss pin driven high (1). this bit has no effect if ssio = 0 or spi configured as a slave spi diagnostic state register the spi diagnostic state register provides obse rvability of internal st ate. this is a read only register used for spi diagnostics. scken?shift clock enable 0 = the internal shift clock enable signal is deasserted 1 = the internal shift clock enable signal is asserted (shift register is updates on next system clock) tcken?transmit clock enable 0 = the internal transmit clock enable signal is deasserted. 1 = the internal transmit clock enable signal is asserted. when this is asserted the serial data out is updated on the next system clock (mosi or miso). spistate?spi state machine defines the current state of th e internal spi state machine. spi baud rate high and low byte registers the spi baud rate high and low byte regist ers combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. when configured as a general purpose timer, the interrupt interval is calcu lated using the following equation: interrupt interval (s) = system clock period (s) brg[15:0] table 67. spi diagnostic state register (spidst) bits 7 6 5 4 3 2 1 0 field scken tcken spistate reset 0 r/w r addr f64h table 68. spi baud rate high byte register (spibrh) bits 7 6 5 4 3 2 1 0 field brh reset 1 r/w r/w addr f66h
ps022517-0508 serial peripheral interface z8 encore! xp ? f0822 series product specification 126 brh = spi baud rate high byte most significant byte, brg[1 5:8], of the spi baud rate generator?s reload value. brl = spi baud rate low byte least significant byte, brg[7:0], of the spi baud rate generator?s reload value. table 69. spi baud rate low byte register (spibrl) bits 7 6 5 4 3 2 1 0 field brl reset 1 r/w r/w addr f67h
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 127 i 2 c controller the i 2 c controller makes the f0822 series pr oducts bus-compatible with the i 2 c proto- col. the i 2 c controller consists of tw o bidirectional bus lines?a serial data signal (sda) and a serial clock signal (scl). features of the i 2 c controller include: ? transmit and receive operation in master mode. ? maximum data rate of 400 kbit/s. ? 7-bit and 10-bit addressing modes for slaves. ? unrestricted number of data bytes transmitted per transfer. the i 2 c controller in the f0822 series products does not operate in slave mode. architecture figure 25 displays the architecture of the i 2 c controller. figure 25. i 2 c controller block diagram sda scl i 2 cctl ishift i 2 cdata i 2 cbrh i 2 cbrl shift load tx/rx state machine baud rate generator receive i 2 cstat register bus i 2 c interrupt
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 128 operation the i 2 c controller operates in master mode to tr ansmit and receive data. only a single master is supported. arbitration between two masters must be accomplished in software. i 2 c supports the follo wing operations: ? master transmits to a 7-bit slave ? master transmits to a 10-bit slave ? master receives from a 7-bit slave ? master receives from a 10-bit slave sda and scl signals i 2 c sends all addresses, data and acknowledge signals over the sda line, most-significant bit first. scl is the common clock for the i 2 c controller. when the sda and scl pin alternate functions are selected for their respective gpio port s, the pins are automatically configured for open -drain operation. the master (i 2 c) is responsible for driving the scl clock signal, although the clock signal becomes skewed by a slow slave device. duri ng the low period of the clock, the slave pulls the scl signal low to suspend the tran saction. the master releases the clock at the end of the low period and notices that the cloc k remains low instead of returning to a high level. when the slave re leases the clock, the i 2 c controller continues the transaction. all data is transferred in bytes and there is no limit to the amount of da ta transferred in one operation. when transmitting data or acknow ledging read data from the slave, the sda signal changes in the middle of the low period of scl and is sampled in the middle of the high period of scl. i 2 c interrupts the i 2 c controller contains four sources of in terrupts?transmit, receive, not acknowl- edge, and baud rate generator. these four inte rrupt sources are combined into a single interrupt request signal to the interrupt controller. the tr ansmit interrupt is enabled by the ien and txi bits of the control register. the receive and not acknowledge interrupts are enabled by the ien bit of the control regist er. brg interrupt is enabled by the birq and ien bits of the control register. not acknowledge interrupts oc cur when a not acknowledg e condition is received from the slave or sent by the i 2 c controller and neither the start or stop bit is set. the not acknowledge event sets the ncki bit of the i 2 c status register and can only be cleared by setting the start or stop bit in the i 2 c control register. when this interrupt occurs, the i 2 c controller waits until either the stop or start bit is set before performing any action. in an isr, the ncki bit should always be checked prior to servicing transmit or receive interrupt conditions because it indicates the trans action is being terminated.
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 129 receive interrupts occur when a byte of data has been r eceived by the i 2 c controller (master reading data from slave). this procedure sets the rdrf bit of the i 2 c status register. the rdrf bit is cleared by reading the i 2 c data register. the rdrf bit is set during the acknowledge phase. the i 2 c controller pauses afte r the acknowledge phase until the receive interrupt is cleare d before performing any other action. transmit interrupts occur when the tdre bit of the i 2 c status register sets and the txi bit in the i 2 c control register is set. transmit interrupts occur un der the following conditions when the transmit data register is empty: ? the i 2 c controller is enabled ? the first bit of the byte of an address is shifting out and the rd bit of the i 2 c status register is deasserted. ? the first bit of a 10-bit address shifts out. ? the first bit of write data shifts out. writing to the i 2 c data register always clears the trde bit to 0. when tdre is asserted, the i 2 c controller pauses at the beginning of the acknowledge cycle of the byte currently shifting out until the data register is written with the next value to send or the stop or start bits are set indicating the curr ent byte is the last one to send. the fourth interrupt source is the brg. if the i 2 c controller is disabl ed (ien bit in the i2cctl register = 0) and the birq bit in the i2cctl register = 1, an interrupt is generated when the br g counts down to 1. this allows the i 2 c baud rate generator to be used by software as a general purpose timer when ien = 0. software control of i 2 c transactions software controls i 2 c transactions by using the i 2 c controller interrupt , by polling the i 2 c status register or by dma. note that not all products include a dma controller. to use interrupts, the i 2 c interrupt must be enabled in th e interrupt controller. the txi bit in the i 2 c control register must be set to enable transmit interrupts. to control transactions by polling, the inte rrupt bits (tdre, rdrf and ncki) in the i 2 c status register should be polled. the tdre bit asserts regardless of the state of the txi bit. either or both transmit and receive data movement can be controlled by the dma controller. the dma controlle r channel(s) must be in itialized to select the i 2 c transmit and receive requests. transmit dma reques ts require that the txi bit in the i 2 c control register be set. a transmit (write) dma operation hangs if th e slave responds with a not acknowledge before the last byte has been sent. a fter receiving the not acknowledge, the i 2 c con- troller sets the ncki bit in the status re gister and pauses until either the stop or note: caution:
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 130 start bits in the control register are set. in order for a receive (read) dma transact ion to send a not ack nowledge on the last byte, the receive dma must be set up to receive n-1 bytes, then software must set the nak bit and receive the last (nth) byte directly. start and stop conditions the master (i 2 c) drives all start and stop signals and initiates all transactions. to start a transaction, the i 2 c controller generates a start condition by pu lling the sda signal low while scl is high. to complete a transaction, the i 2 c controller generates a stop condition by creating a low-to-hig h transition of the sda signal while the scl signal is high. the start and stop bits in the i 2 c control register cont rol the sending of the start and stop conditions. a master is also a llowed to end one transaction and begin a new one by issuing a restart. this is accomplished by setting the start bit at the end of a transaction, rather than the stop bit. the start condition not sent until the start bit is set and data has be en written to the i 2 c data register. master write and read transactions the following sections provide a recommended procedure for performing i 2 c write and read transactions from the i 2 c controller (master) to slave i 2 c devices. in general soft- ware should rely on the tdre , rdrf and ncki bits of the status register (these bits generate interrupts) to initiate software ac tions. when using interrupts or dma, the txi bit is set to start each transaction and cleare d at the end of each transaction to eliminate a ?trailing? transmit interrupt. caution should be used in using the ack stat us bit within a transa ction because it is diffi- cult for software to tell when it is updated by hardware. when writing data to a slave, the i 2 c pauses at the beginning of the acknowledge cycle if the data register has not been written with th e next value to be se nt (tdre bit in the i 2 c status register equal to 1). in this scenario where software is not keeping up with the i 2 c bus (tdre asserted longer than one byte time), the acknowledge clock cycle for byte n is delayed until the data register is written with byte n + 1, and appear s to be grouped with the data clock cycles for byte n + 1. if e ither the start or stop bit is set, the i 2 c does not pause prior to the acknowledge cycl e because no additional data is sent. when a not acknowledg e condition is received during a write (either during the address or data phases), the i 2 c controller generates the not ac knowledge interrupt (ncki = 1) and pause until either the stop or start b it is set. unless the not acknowledge was received on the last byte, th e data register will already ha ve been written with the next address or data byte to send. in this case th e flush bit of the control register should be set at the same time the stop or start bit is set to remove the stale transmit data and enable subsequent transmit interrupts. note:
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 131 when reading data from the slave, the i 2 c pauses after the data acknowledge cycle until the receive interrupt is serviced and the rdrf bit of the status register is cleared by reading the i 2 c data register. once the i 2 c data register has been read, the i 2 c reads the next data byte. address only transacti on with a 7-bit address in the situation where software determines if a slave with a 7-bit address is responding without sending or receiving data, a transactio n can be done which only consists of an address phase. figure 26 on page 131 displays this ?addr ess only? transaction to determine if a slave with a 7-bit address will acknowledg e. as an example, th is transaction can be used after a ?write? has been done to a eeprom to de termine when the eeprom com- pletes its internal write operation and is once again responding to i 2 c transactions. if the slave does not acknowledge, the transaction is repeated until the slave does acknowl- edge. figure 26. 7-bit address only transaction format follow the steps below for an address only transaction to a 7-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty (tdre = 1) 4. software responds to the tdre bit by writing a 7-bit slave address plus write bit (=0) to the i 2 c data register. as an alternative this could be a read operation instead of a write operation. 5. software sets the start and stop bits of the i 2 c control register and clears the txi bit. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. software polls the stop bit of the i 2 c control register. hardware deasserts the stop bit when the address only transaction is completed. 9. software checks the ack bit of the i 2 c status register. if the slave acknowledged, the ack bit is equal to 1. if the slave does not acknowledge, the ack bit is equal to 0. the ncki interrupt does not occur in the not acknowledge case because the stop bit was set. s slave address w = 0 a/a p
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 132 write transaction wi th a 7-bit address figure 27 displays the data transfer format for a 7-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 27. 7-bit addressed slave data transfer format follow the steps below for a transmit operation to a 7-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty. 4. software responds to the tdre bit by writing a 7-bit slave address plus write bit (=0) to the i 2 c data register. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address has been shifted ou t by the sda signal, the transmit interrupt is asserted (tdre = 1). 9. software responds by writing the transmit data into the i 2 c data register. 10. the i 2 c controller shifts the rest of the ad dress and write bit out by the sda signal. 11. if the i 2 c slave sends an acknowledge (by pullin g the sda signal low) during the next high period of scl the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 12 . if the slave does not acknowledge, the not ac knowledge interrupt occurs (ncki bit is set in the status register, ack bit is cleared). software responds to the not acknowledge interrupt by setting the stop an d flush bits and clearing the txi bit. the i 2 c controller sends the stop condition on the bus and clears the stop and ncki bits. the transaction is comp lete (ignore following steps). 12. the i 2 c controller loads the contents of the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the data out of usin g the sda signal. after the first bit is sent, the transmit interrupt is asserted. s slave address w = 0 a data a data a data a/a p/s
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 133 14. if more bytes remain to be sent, return to step 9 . 15. software responds by setting the stop bit of the i 2 c control register (or start bit to initiate a new transaction). in th e stop case, software clears the txi bit of the i 2 c control register at the same time. 16. the i 2 c controller completes transmission of the data on the sda signal. 17. the slave can either acknowledge or not acknowledge the last byte. because either the stop or start bit is already set , the ncki interrupt does not occur. 18. the i 2 c controller sends the stop (or restart) condition to the i 2 c bus. the stop or start bit is cleared. address only transacti on with a 10-bit address in the situation where software wants to de termine if a slave with a 10-bit address is responding without sending or receiving data, a transaction is done which only consists of an address phase. figure 28 displays this ?address only? tran saction to determine if a slave with 10-bit address will acknowledge. as an example, this transaction is used after a ?write? has been done to a eeprom to dete rmine when the eeprom completes its inter- nal write operation and is once again respondi ng to i2c transactions. if the slave does not acknowledge the transaction is repeated un til the slave is able to acknowledge. figure 28. 10-bit address only transaction format follow the steps below for an address only transaction to a 10-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty (tdre = 1) 4. software responds to the tdre interrupt by writing the fi rst slave address byte. the least-significant bit must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address is shifted out by the sda signal, the transmit interrupt is asserted. s slave address 1st 7 bits w = 0 a/a slave address 2nd byte a/a p
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 134 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out the sda signal. 11. if the i 2 c slave sends an acknowle dge by pulling the sda signal low during the next high period of scl the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 12 . if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software response to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i2c controller sends the stop c ondition on the bus and cl ears the stop and ncki bits. the transaction is comp lete (ignore following steps). 12. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (2nd byte of address). 13. the i 2 c controller shifts the second address byte out the sda signal. after the first bit has been sent, the transmit interrupt is asserted. 14. software responds by setting the stop bit in the i 2 c control regist er. the txi bit can be cleared at the same time. 15. software polls the stop bit of the i 2 c control register. hardware deasserts the stop bit when the transaction is comp leted (stop condition has been sent). 16. software checks the ack bit of the i 2 c status register. if the slave acknowledged, the ack bit is equal to 1. if the slave does not acknowledge, the ack bit is equal to 0. the ncki interrupt do not o ccur because the stop bit was set. write transaction wi th a 10-bit address figure 29 displays the data transfer format for a 10-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 29. 10-bit addressed slave data transfer format the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the read/write control bit (=0). the transmit oper ation is carried out in the same manner as 7- bit addressing. s slave address 1st 7 bits w = 0 a slave address 2nd byte a data a data a/a p/s
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 135 follow the steps below for a transmit op eration on a 10-bit addressed slave: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts because the i 2 c data register is empty. 4. software responds to the tdre interrupt by writing the firs t slave address byte to the i 2 c data register. the least-significant b it must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address is shifted out by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out the sda signal. 11. if the i 2 c slave acknowledges the fi rst address byte by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 12 . if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i2c controller sends the stop c ondition on the bus and cl ears the stop and ncki bits. the transaction is comple te (ignore the following steps). 12. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the second address byte out the sda signal. after the first bit has been sent, the transmit interrupt is asserted. 14. software responds by writing a data byte to the i 2 c data register. 15. the i 2 c controller completes shiftin g the contents of the shift register on the sda signal. 16. if the i 2 c slave sends an acknowle dge by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 17 . if the slave does not acknowledge the second ad dress byte or one of the data bytes, the
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 136 i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi b it. the i2c controller sends the stop condition on the bus and clears the stop and ncki bits. the tran saction is complete (ignore the following steps). 17. the i 2 c controller shifts the data out by the s da signal. after the first bit is sent, the transmit interrupt is asserted. 18. if more bytes remain to be sent, return to step 14 . 19. if the last byte is currently being sent, software sets the stop bit of the i 2 c control register (or start bit to initiate a new tran saction). in the stop case, software also clears the txi bit of the i 2 c control register at the same time. 20. the i 2 c controller completes transmission of the last data byte on the sda signal. 21. the slave can either acknowledge or not acknowledge the last byte. because either the stop or start bit is already set , the ncki interrupt does not occur. 22. the i 2 c controller sends the stop (or restart) condition to the i 2 c bus and clears the stop (or start) bit. read transaction wi th a 7-bit address figure 30 displays the data transfer format for a read operation to a 7-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data tr ansferred from the slaves to the i 2 c controller. figure 30. receive data transfer format for a 7-bit addressed slave follow the steps below for a read op eration to a 7-bit addressed slave: 1. software writes the i 2 c data register with a 7-bit slave address plus the read bit (=1). 2. software asserts the start bit of the i 2 c control register. 3. if this is a single byte transfer, software asserts the nak bit of the i 2 c control register so that after the first byte of data has been read by the i 2 c controller, a not acknowledge is sent to the i 2 c slave. 4. the i 2 c controller sends the start condition. 5. the i 2 c controller shifts the address a nd read bit out the sda signal. 6. if the i 2 c slave acknowledges the address by pul ling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 7 . s slave address r = 1 a data adata a p/s
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 137 if the slave does not acknowledge, the not ac knowledge interrupt occurs (ncki bit is set in the status register, ack bit is cleared). software responds to the not acknowledge interrupt by setting the stop bit and clearing the txi bit. the i2c controller sends the stop co ndition on the bus and clears the stop and ncki bits. the transaction is complete (ignore the following steps). 7. the i 2 c controller shifts in th e byte of data from the i 2 c slave on the sda signal. the i 2 c controller sends a not acknowledge to the i 2 c slave if the nak bit is set (last byte), else it sends an acknowledge. 8. the i 2 c controller asserts the rece ive interrupt (rdrf bit set in the status register). 9. software responds by reading the i 2 c data register which clears the rdrf bit. if there is only one more byte to receive, set the nak bit of the i 2 c control register. 10. if there are more bytes to transfer, return to step 7. 11. after the last byte is shifted in, a not acknowledge interrupt is generated by the i 2 c controller. 12. software responds by setting the stop bit of the i 2 c control register. 13. a stop condition is sent to the i 2 c slave, the stop and ncki bits are cleared. read transaction wi th a 10-bit address figure 31 displays the read transaction format fo r a 10-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 31. receive data format for a 10-bit addressed slave the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the write control bit. follow the steps below for the data transfer procedure for a read operation to a 10-bit addressed slave: 1. software writes 11110b followed by the two address bits and a 0 (write) to the i 2 c data register. 2. software asserts the start and txi bits of the i 2 c control register. 3. the i 2 c controller sends the start condition. 4. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. s slave address 1st 7 bits w=0 a slave address 2nd byte a s slave address 1st 7 bits r=1 a data adata a p
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 138 5. after the first bit has been shifted out, a transmit interrupt is asserted. 6. software responds by writing the lowe r eight bits of address to the i 2 c data register. 7. the i 2 c controller completes shifting of th e two address bits and a 0 (write). 8. if the i 2 c slave acknowledges the fi rst address byte by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 9 . if the slave does not acknowledge the first address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i2c controller sends the stop c ondition on the bus and cl ears the stop and ncki bits. the transaction is comp lete (ignore following steps). 9. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (second address byte). 10. the i 2 c controller shifts out the second address by te. after the first bit is shifted, the i 2 c controller generate s a transmit interrupt. 11. software responds by setting the start bit of the i 2 c control register to generate a repeated start and by clearing the txi bit. 12. software responds by writing 11110b followed by the 2-bit slave address and a 1 (read) to the i 2 c data register. 13. if only one byte is to be read , software sets the nak bit of the i 2 c control register. 14. after the i 2 c controller shifts out the 2nd address byte, the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl, the i 2 c controller sets the ack bit in the i 2 c status register. continue with step 15. if the slave does not acknowledge the second address byte, the i 2 c controller sets the ncki bit and clears the ack bit in the i 2 c status register. software responds to the not acknowledge interrupt by setting the stop and flush bits and clearing the txi bit. the i2c controller sends the stop c ondition on the bus and cl ears the stop and ncki bits. the transaction is comple te (ignore the following steps). 15. the i 2 c controller sends the re peated start condition. 16. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register (third address transfer). 17. the i 2 c controller sends 11110b followed by the two most significant bits of the slave read address and a 1 (read). 18. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. if the slave were to not acknowledge at this point (this should not happen because the slave did acknowledge the firs t two address bytes), softwa re would respond by setting the stop and flush bits and clearing th e txi bit. the i2c controller sends the
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 139 stop condition on the bus and clears the stop and ncki bits. the transaction is complete (ignore th e following steps). 19. the i 2 c controller shifts in a byte of data from the i 2 c slave on the sda signal. the i 2 c controller sends a not acknowledge to the i 2 c slave if the nak bit is set (last byte), else it sends an acknowledge. 20. the i 2 c controller asserts the rece ive interrupt (rdrf bit set in the status register). 21. software responds by reading the i 2 c data register which clears the rdrf bit. if there is only one more byte to receive, set the nak bit of the i 2 c control register. 22. if there are one or more bytes to transfer, return to step 19 . 23. after the last byte is shifted in, a not acknowledge interrupt is generated by the i 2 c controller. 24. software responds by setting the stop bit of the i 2 c control register. 25. a stop condition is sent to the i 2 c slave and the stop and ncki bits are cleared. i 2 c control register definitions i 2 c data register the i 2 c data register ( table 70 ) holds the data that is to be loaded into the i 2 c shift reg- ister during a write to a slave. this register also holds data that is loaded from the i 2 c shift register during a read from a slave. the i 2 c shift register is not accessible in the register file address space, but is used only to buffer incoming and outgoing data. table 70. i 2 c data register (i2cdata) bits 7 6 5 4 3 2 1 0 field data reset 0 r/w r/w addr f50h
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 140 i 2 c status register the read-only i 2 c status register ( table 71 ) indicates the status of the i 2 c controller. tdre?transmit data register empty when the i 2 c controller is enabled, this bit is 1 when the i 2 c data register is empty. when this bit is set, an in terrupt is generated if the tx i bit is set, except when the i 2 c controller is shifting in data during the rece ption of a byte or when shifting an address and the rd bit is set. this bit is cleared by writing to the i2cdata register. rdrf?receive data register full this bit is set = 1 when the i 2 c controller is en abled and the i 2 c controller has received a byte of data. when asserted, this bit causes the i 2 c controller to generate an interrupt. this bit is cleared by reading the i 2 c data register (unless the read is performed using execution of the ocd?s read register command). ack?acknowledge this bit indicates the st atus of the acknowledge for the last byte transmitted or received. when set, this bit indicates that an acknowle dge occurred for the last byte transmitted or received. this bit is cleared when ien = 0 or when a not acknowledge occurred for the last byte transmitted or received. it is not reset at the beginning of each transaction and is not reset when this register is read. software must be cautious in making decisi ons based on this bit within a transaction because software cannot tell wh en the bit is updated by ha rdware. in the case of write transactions, the i 2 c pauses at the beginning of the acknowledge cycle if the next transmit data or address byte has not been written (tdre = 1) and stop and start = 0. in this case the ack bit is not updat ed until the transmit in terrupt is serviced and the acknowledge cycle for the previous byte completes. for examples on usage of the ack bit, see address only transaction with a 7-bit address on page 131 and address only transaction w ith a 10-bit address on page 133. 10b?10-bit address this bit indicates whether a 10-bit or 7-b it address is being transmitted. after the start bit is set, if the five most-significant bits of the address are 11110b , this bit is set. when set, it is reset once the first byte of the address has been sent. table 71. i 2 c status register (i2cstat) bits 7 6 5 4 3 2 1 0 field tdre rdrf ack 10b rd tas dss ncki reset 10 r/w r addr f51h caution:
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 141 rd?read this bit indicates the direction of transfer of the data. it is active high during a read. the status of this bit is determined by the least-significant bit of the i 2 c shift register after the start bit is set. tas?transmit address state this bit is active high wh ile the address is being shifted out of the i 2 c shift register. dss?data shift state this bit is active high while data is being sh ifted to or from the i 2 c shift register. ncki?nack interrupt this bit is set high when a not acknowledge condition is rece ived or sent and neither the start nor the stop bit is active. when set, this bit ge nerates an interrupt that can only be cleared by setting the start or stop bit, allowing you to sp ecify whether you want to perform a stop or a repeated start . i 2 c control register the i 2 c control register ( table 72 ) enables the i 2 c operation. ien?i 2 c enable 1 = the i 2 c transmitter and receiver are enabled. 0 = the i 2 c transmitter and receiver are disabled. start?send start condition this bit sends the start condition. on ce asserted, it is cleared by the i 2 c controller after it sends the start condition or if the ien bit is deasserted. if this bit is 1, it cannot be cleared to 0 by writing to the register. after this bit is set, the start condition is sent if there is data in the i 2 c data or i 2 c shift register. if there is no data in one of these regis- ters, the i 2 c controller waits until the data register is written. if this bit is set while the i 2 c controller is shifting out data, it generates a start condition after the byte shifts and the acknowledge ph ase completes. if the stop bit is also set, it also waits until the stop condition is sent before sending the start condition. stop?send stop condition this bit causes the i 2 c controller to issue a stop co ndition after the byte in the i 2 c shift register has completed transmission or after a by te is received in a receive operation. once table 72. i 2 c control register (i2cctl) bits 7 6 5 4 3 2 1 0 field ien start stop birq txi nak flush filten reset 0 r/w r/w r/w1 r/w1 r/w r/w r/w1 w1 r/w addr f52h
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 142 set, this bit is reset by the i 2 c controller after a stop condition is sent or by deasserting the ien bit. if this bit is 1, it cannot be cleared to 0 by writing to the register. birq?baud rate generator interrupt request this bit allows the i 2 c controller to be used as an additional timer when the i 2 c controller is disabled. this bit is ignored when the i 2 c controller is enabled. 1 = an interrupt occurs every tim e the brg counts down to one. 0 = no brg interrupt occurs. txi?enable tdre interrupts this bit enables the tran smit interrupt when the i 2 c data register is empty (tdre = 1). 1 = transmit interrupt (and dm a transmit request) is enabled. 0 = transmit interrupt (and dma transmit request) is disabled. nak?send nak this bit sends a not acknowledg e condition after the next byte of data is read from the i 2 c slave. once asserted, it is deasserted after a not acknowledge is sent or the ien bit is deasserted. if this bit is 1, it cannot be cleared to 0 by writing to the register. flush?flush data setting this bit to 1 clears the i 2 c data register and sets the tdre bit to 1. this bit allows flushing of the i 2 c data register when a not acknowle dge interrupt is received after the data has been sent to the i 2 c data register. reading th is bit always returns 0. filten?i 2 c signal filter enable this bit enables low-pass dig ital filters on the sda and scl input signals. these filters reject any input pulse with periods less than a full system clock cycle. the filters introduce a 3-system clock cycle latency on the inputs. 1 = low-pass filters are enabled. 0 = low-pass filters are disabled.
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 143 i 2 c baud rate high and low byte registers the i 2 c baud rate high and low by te registers (tables 73 and 73) combine to form a 16- bit reload value, brg[15:0], for the i 2 c baud rate generator. wh en configured as a gen- eral purpose timer, the interrupt interval is calculated using the following equation: interrupt interval (s) = system clock period (s) brg[15:0] brh = i 2 c baud rate high byte most significant byte , brg[15:8], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c diagnostic control register is set to 1, a read of the i2cbrh register returns the current value of the i 2 c baud rate counter[15:8]. brl = i 2 c baud rate low byte least significant byte, brg[7:0], of the i 2 c baud rate generator?s reload value. if the diag bit in the i 2 c diagnostic control register is set to 1, a read of the i2cbrl register returns the current value of the i 2 c baud rate counter [7:0]. i 2 c diagnostic state register the i 2 c diagnostic state register ( table 75 ) provides observability of internal state. this is a read only register used for i 2 c diagnostics and manufacturing test. table 73. i 2 c baud rate high byte register (i2cbrh) bits 7 6 5 4 3 2 1 0 field brh reset ffh r/w r/w addr f53h table 74. i 2 c baud rate low byte register (i2cbrl) bits 7 6 5 4 3 2 1 0 field brl reset ffh r/w r/w addr f54h note: note:
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 144 sclin ?value of serial clock input signal sdain ?value of the serial data input signal stpcnt ?value of the internal stop count control signal txrxstate ?value of the internal i 2 c state machine table 75. i 2 c diagnostic state register (i2cdst) bits 7 6 5 4 3 2 1 0 field sclin sdain stpcnt txrxstate reset x0 r/w r addr f55h txrxstate state description 0_0000 idle state 0_0001 start state 0_0010 send/receive data bit 7 0_0011 send/receive data bit 6 0_0100 send/receive data bit 5 0_0101 send/receive data bit 4 0_0110 send/receive data bit 3 0_0111 send/receive data bit 2 0_1000 send/receive data bit 1 0_1001 send/receive data bit 0 0_1010 data acknowledge state 0_1011 second half of data acknowledg e state used only for not acknowledge 0_1100 first part of stop state 0_1101 second part of stop state 0_1110 10-bit addressing: acknowledge state for 2nd address byte 7-bit addressing: address acknowledge state 0_1111 10-bit address: bit 0 (least sign ificant bit) of 2nd address byte 7-bit address: bit 0 (least significant bit) (r/w) of address byte 1_0000 10-bit addressing: bit 7 (most significant bit) of 1st address byte 1_0001 10-bit addressing: bit 6 of 1st address byte 1_0010 10-bit addressing: bit 5 of 1st address byte 1_0011 10-bit addressing: bit 4 of 1st address byte 1_0100 10-bit addressing: bit 3 of 1st address byte 1_0101 10-bit addressing: bit 2 of 1st address byte 1_0110 10-bit addressing: bit 1 of 1st address byte
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 145 i 2 c diagnostic c ontrol register the i 2 c diagnostic register ( table 76 ) provides control over diagnostic modes. this register is a read/write register used for i 2 c diagnostics. diag = diagnostic control bit?selects read back value of the baud rate reload registers. 0 = normal mode. reading the baud rate high and low byte registers returns the baud rate reload value. 1 = diagnostic mode. reading the baud rate high and low byte registers returns the baud rate counter value. 1_0111 10-bit addressing: bit 0 (r/w) of 1st address byte 1_1000 10-bit addressing: acknowledge state for 1st address byte 1_1001 10-bit addressing: bit 7 of 2nd address byte 7-bit addressing: bit 7 of address byte 1_1010 10-bit addressing: bit 6 of 2nd address byte 7-bit addressing: bit 6 of address byte 1_1011 10-bit addressing: bit 5 of 2nd address byte 7-bit addressing: bit 5 of address byte 1_1100 10-bit addressing: bit 4 of 2nd address byte 7-bit addressing: bit 4 of address byte 1_1101 10-bit addressing: bit 3 of 2nd address byte 7-bit addressing: bit 3 of address byte 1_1110 10-bit addressing: bit 2 of 2nd address byte 7-bit addressing: bit 2 of address byte 1_1111 10-bit addressing: bit 1 of 2nd address byte 7-bit addressing: bit 1 of address byte table 76. i 2 c diagnostic control register (i2cdiag) bits 7 6 5 4 3 2 1 0 field reserved diag reset 0 r/w rr/w addr f56h txrxstate state description
ps022517-0508 i2c controller z8 encore! xp ? f0822 series product specification 146
ps022517-0508 analog-to-digital converter z8 encore! xp ? f0822 series product specification 147 analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to a 10-bit binary number. the features of the sigma-delta adc include: ? five analog input sources are multiplexed with gpio ports. ? interrupt upon conversion complete. ? internal voltage re ference generator. the adc is available only in the z8f0822, z8f0821, z8f0422, z8f0421, z8r0822, z8r0821, z8r0422 and z8r0421 devices. architecture figure 32 displays the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the adc. the ad c converts an analog input signal to its digital representation. the 5-input analog mu ltiplexer selects one of the 5 analog input sources. the adc requires an input reference voltage for the conversion. the voltage ref- erence for the conversion can be input through the external vref pin or generated inter- nally by the voltage reference generator. figure 32. analog-to-digital converter block diagram analog-to-digital converter ana0 ana1 ana2 ana3 ana4 analog input multiplexer anain[3:0] internal voltage reference generator vref analog input reference input irq
ps022517-0508 analog-to-digital converter z8 encore! xp ? f0822 series product specification 148 operation automatic power-down if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powere d-down. from this power-down state, the adc requires 40 system clock cycles to power-up. the adc powers up when a conversion is requested using the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. follow the steps below for setting up the adc and initiating a single- shot conversion: 1. enable the desired analog inputs by config uring the gpio pins for alternate function. this configuration disables the digital input and output drivers. 2. write to the adc control register to co nfigure the adc and begin the conversion. the bit fields in the adc control register is written simultaneously: ? write to the anain[3:0] field to select one of the 5 analog input sources. ?clear cont to 0 to select a single-shot conversion. ? write to the vref bit to enable or disable the in ternal voltage reference generator. ?set cen to 1 to start the conversion. 3. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. when the conversion is complete, the adc control logic performs the following operations: ? 10-bit data result written to {adcd_h[7:0], adcd_l[7:6]}. ? cen resets to 0 to indicate th e conversion is complete. ? an interrupt request is sent to the interrupt controller. 5. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion, the adc continuously performs an analog-to-digital conversion on the selected analog input. e ach new data value over-writes the previous value stored in the adc data registers. an in terrupt is generated after each conversion.
ps022517-0508 analog-to-digital converter z8 encore! xp ? f0822 series product specification 149 in continuous mode, ensure that adc updates are lim ited by the input signal bandwidth of the adc and the latency of the adc and its digital fil- ter. step changes at the input are no t seen at the next output from the adc. the response of the adc (in all modes) is limited by the input signal band- width and the latency. follow the steps below for setting up the adc and initiating con tinuous conversion: 1. enable the desired analog input by config uring the gpio pins for alternate function. this disables the digital input and output driver. 2. write to the adc control register to co nfigure the adc for continuous conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select one of the 5 analog input sources. ?set cont to 1 to select continuous conversion. ? write to the vref bit to enable or disable the in ternal voltage re ference generator. ?set cen to 1 to start the conversions. 3. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the conversion is complete. 4. thereafter, the adc writes a new 10-bit data result to {adcd_h[7:0], adcd_l[7:6]} every 256 system clock cycles. an interrupt request is sent to the interrupt controller when e ach conversion is complete. 5. to disable continuous conversion, clear the cont bit in the adc control register to 0. caution:
ps022517-0508 analog-to-digital converter z8 encore! xp ? f0822 series product specification 150 adc control register definitions adc control register the adc control register selects the analog input channel and initiates the analog-to-digital conversion. cen?conversion enable 0 = conversion is complete. writing a 0 pr oduces no effect. the adc automatically clears this bit to 0 wh en a conversion has been completed. 1 = begin conversion. writing a 1 to this b it starts a conversion. if a conversion is already in progress , the conversion restarts. this bit remains 1 until the conversion is complete. reserved?must be 0 vref 0 = internal reference generator enabled. the vref pin must be left unconnected or capacitively coupled to analog ground (avss). 1 = internal voltage referen ce generator disabled. an exte rnal voltage reference must be provided through the vref pin. cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles. 1 = continuous conversion. adc data updated every 256 system clock cycles. anain?analog input select these bits select the analog inpu t for conversion. not all port pins in this list are available in all packages for z8 encore! xp ? f0822 series. see signal and pin descriptions for information regarding the port pins available with each package style. do not enable unavailable analog inputs. 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 table 77. adc control register (adcctl) bits 7 6 5 4 3 2 1 0 field cen reserved vref cont anain[3:0] reset 01 0 r/w r/w addr f70h
ps022517-0508 analog-to-digital converter z8 encore! xp ? f0822 series product specification 151 0101 = reserved 011x = reserved 1xxx = reserved adc data high byte register the adc data high byte register contains th e upper eight bits of the 10-bit adc output. during a single-shot conversion, this value is invalid. access to the adc data high byte register is read-only. the full 10-bit adc result is given by {adcd_h[7:0], adcd_l[7:6]}. reading the adc data high by te register latches data in the adc low bits register. adcd_h?adc data high byte this byte contains the upper eight bits of the 10-bit adc output. these bits are not valid during a single-shot conversion. during a co ntinuous conversion, the last conversion output is held in this register. th ese bits are undefined after a reset. adc data low bits register the adc data low bits register contains the lower two bits of the conversion value. the data in the adc data low bits register is latched each time the adc data high byte register is read. reading this register always returns the lower two bi ts of the conversion last read into the adc high byte register. access to the adc data low bits register is read-only. the full 10-bit adc result is given by {adcd_h[7:0], adcd_l[7:6]}. table 78. adc data high byte register (adcd_h) bits 7 6 5 4 3 2 1 0 field adcd_h reset x r/w r addr f72h table 79. adc data low bits register (adcd_l) bits 7 6 5 4 3 2 1 0 field adcd_l reserved reset x r/w r addr f73h
ps022517-0508 analog-to-digital converter z8 encore! xp ? f0822 series product specification 152 adcd_l?adc data low bits these are the least significant two bits of th e 10-bit adc output. these bits are undefined after a reset. reserved these bits are reserved and are always undefined.
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 153 flash memory the products in z8 encore! xp ? f0822 series feature either 8 kb (8192) or 4 kb (4096) bytes of flash memory with read/write/e rase capability. the flash memory is pro- grammed and erased in-circuit by either user code or through the ocd. the flash memory array is arranged in 512-byte per page. the 512-byte page is the minimum flash block size that can be erased . the flash memory is divided into eight sectors which is protected from programming an d erase operations on a per sector basis. table 80 describes the flash memory configuration for each device in the z8f082x family. table 81 lists the sector address ranges. figure 33 on page 154 displays the flash memory arrangement. table 80. flash memory configurations part number flash size number of pages flash memory addresses sector size number of sectors pages per sector z8f08xx 8 kb (8192) 16 0000h - 1fffh 1 kb (1024) 8 2 z8f04xx 4 kb (4096) 8 0000h - 0fffh 0.5 kb (512) 8 1 table 81. flash memory sector addresses sector number flash sector address ranges z8f04xx z8f08xx 0 0000h-01ffh 0000h-03ffh 1 0200h-03ffh 0400h-07ffh 2 0400h-05ffh 0800h-0bffh 3 0600h-07ffh 0c00h-0fffh 4 0800h-09ffh 1000h-13ffh 5 0a00h-0bffh 1400h-17ffh 6 0c00h-0dffh 1800h-1bffh 7 0e00h-0fffh 1c00h-1fffh
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 154 figure 33. flash memory arrangement information area table 82 on page 155 describes the z8 encore! xp ? f0822 series information area. this 512-byte information area is acce ssed by setting bit 7 of the page select register to 1. when access is enabled, the information area is mapped into flash memory and overlays the 512 bytes at addresses fe00h to ffffh . when the information area access is enabled, ldc instructions return data from the information area. cp u instruction fetches always comes from flash memory regardless of the information area access bit. access to the information area is read-only. 8 kb flash program memory 0000h 16 pages 512 bytes per page 01ffh 0200h 03ffh 1c00h 1dffh 1e00h 1fffh 0400h 05ffh 1a00h 1bffh addresses
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 155 operation the flash controller provides the proper sign als and timing for byte programming, page erase, and mass erase of the flash memory. the flash controller contains a protection mechanism, using the flash control register (fctl), to prevent accidental programming or erasure. the following subsections provide details on the various operations (lock, unlock, sector protect, byte programm ing, page erase, and mass erase). timing using the flash frequency registers before performing a program or erase operat ion on the flash memory, you must first configure the flash frequency high and lo w byte registers. the flash frequency registers allow programming and erasure of the flash with system clock frequencies ranging from 20 khz through 20 mhz (the va lid range is limited to the device operating frequencies). the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit flash frequency value must contain the system clock frequency in khz. this value is calculated using the following equation: flash programming and erasure are not supported for system clock fre- quencies below 20 khz, above 20 mhz, or outside of the device operating frequency range. the flash frequency high and low byte registers must be loaded with the correct value to insure proper flash programming and erase operations. table 82. z8 encore! xp ? f0822 series information area map flash memory address (hex) function fe00h-fe3fh reserved fe40h-fe53h part number 20-character ascii alphanumeric code left justified and filled with zeros fe54h-ffffh reserved ffreq[15:0] system clock frequency (hz) 1000 ------------------------------------------------------------------------------- = caution:
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 156 flash read protection the user code contained within the flash me mory can be protected from external access. programming the flash read protect option b it prevents reading of user code by the ocd or by using the flash controller byp ass mode. for more information, see option bits on page 163 and on-chip debugger on page 171. flash write/erase protection z8 encore! xp ? f0822 series provides several levels of protection against accidental pro- gram and erasure of the flash memory contents. this protection is provided by the flash controller unlock mechanism, the flash sector protect register, and the flash write pro- tect option bit. flash controller unlock mechanism at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory , the flash controller must be unlocked. after unlocking the flash controller, the flash can be programmed or erased. any value written by user code to the flas h control register or page select register out of sequence locks the flash controller. follow the steps below to unlock th e flash controller from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write the page to be programmed or erased to the page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the pa ge written in step 2 to the page select register. flash sector protection the flash sector protect register is configur ed to prevent sectors from being programmed or erased. once a sector is protected, it cann ot be unprotected by user code. the flash sector protect register is cleared after reset and any previously written protection values is lost. user code must write this register in the initialization ro utine if enable sector protection is desired. the flash sector protect register shares its register file address with the page select register. the flash sector protect register is accessed by writing the flash control register with 5eh . after the flash sector protect register is selected, it can be accessed at the page select register address. when th e user code writes the flash sector protect register, bits can only be set to 1. sectors ca n be protected, but not unprotected, using reg- ister write operations. wr iting a value other than 5eh to the flash control register dese- lects the flash sector protect register and re -enables access to the page select register.
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 157 follow the steps below to setup the flash sector protect register from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write 5eh to the flash control register to select the flash sector protect register. 3. read and/or write the flash sector protect register which is now at register file address ff9h . 4. write 00h to the flash control register to return the flash controller to its reset state. flash write protection option bit the flash write protect option bit can block all program and erase operations from user code. for more information, see option bits on page 163. byte programming when the flash controller is unlocked, writes to flash memory from user code programs a byte into the flash if the address is locate d in the unlocked page. an erased flash byte contains all 1s ( ffh ). the programming operation is used to change bits from 1 to 0. to change a flash bit (or multiple bits) from ze ro to one requires a page erase or mass erase operation. byte programming is accomp lished using the ez8 cpu?s ldc or ldci instructions. refer to ez8 cpu core user manual (um0128) for a description of the ldc and ldci instructions. while the flash controller programs the flas h memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to op erate. interrupts that occur when a program- ming operation is in progress are serviced once the programming op eration is complete. to exit programming mode and lo ck the flash controller, write 00h to the flash control register. user code cannot program flash memory on a page that is located in a protected sector. when user code writes memory locations, only addresses located in the unlocked page are programmed. memory writes outside of the unlocked page are ignored. each memory location must not be programmed more than twice before an erase occurs. follow the steps below to program the flash from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write the page of memory to be pr ogrammed to the page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. caution:
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 158 5. re-write the pa ge written in step 2 to the page select register. 6. write flash memory using ldc or ldci instructions to program the flash. 7. repeat step 6 to program additional memory locations on th e same page. 8. write 00h to the flash control register to lock the flash controller. page erase flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the page select register identifies the page to be erased. while the flash cont roller executes the page erase operation, the ez8 cpu idles but the system cl ock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. interrupts that occur when the page erase operation is in progress are serviced once the page erase operation is complete. when the page erase operation is complete, the flash controller returns to its locked state. only pages located in unprotected sectors can be erased. follow the steps below to perform a page erase operation: 1. write 00h to the flash control register to reset the flash controller. 2. write the page to be erased to the page select register. 3. write the first unlock command 73h to the flash control register. 4. write the second unlock command 8ch to the flash control register. 5. re-write the pa ge written in step 2 to the page select register. 6. write the page erase command 95h to the flash control register. mass erase the flash memory cannot be mass erased by user code. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster programming algorithms by controlling the flash programming signals directly. flash controller bypass is recommended for gang programming applications and large volume customers who do not require in-c ircuit programming of the flash memory. for more information on bypassing the flash controller, refer to third-party flash pro- gramming support for z8 encore! xp, available for download at www.zilog.com .
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 159 flash controller beh avior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the ocd: ? the flash write protect option bit is ignored ? the flash sector protect register is ignored for programming and erase operations ? programming operations are not limited to the page selected in the page select register ? bits in the flash sector protect register can be written to 1 or 0 ? the second write of the page select regist er to unlock the flash controller is not necessary ? the page select register is written when the flash controller is unlocked ? the mass erase command is enabled flash control register definitions flash control register the flash control register ( table 83 ) is used to unlock the flash controller for program- ming and erase operations, or to select the flash sector protect register. the write-only flash control register shares its register f ile address with the read-only flash status register. fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command. 63h = mass erase command 5eh = flash sector protect register select. * all other commands, or any command out of sequence, lock the flash controller. table 83. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 0 r/w w addr ff8h
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 160 flash status register the flash status register ( table 84 ) indicates the current state of the flash controller. this register can be read at any time. the r ead-only flash status register shares its reg- ister file address with the write-only flash control register. reserved these bits are reserved and must be 0. fstat?flash controller status 00_0000 = flash controller locked. 00_0001 = first unlock command received. 00_0010 = second unlock command received. 00_0011 = flash controller unlocked. 00_0100 = flash sector protect register selected. 00_1xxx = program operation in progress. 01_0xxx = page erase operation in progress. 10_0xxx = mass erase operation in progress. page select register the page select (fps) register ( table 85 ) selects the flash memory page to be erased or programmed. each flash page contains 512 by tes of flash memory. during a page erase operation, all flash memory lo cations with the 7 most significant bits of the address given by the page field are erased to ffh . the page select register shares its register file address with the flash sector protect register. the page select register cannot be accessed when the flash sector protect register is enabled. table 84. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 0 r/w r addr ff8h table 85. page select register (fps) bits 7 6 5 4 3 2 1 0 field info_en page reset 0 r/w r/w addr ff9h
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 161 info_en?information area enable 0 = information area is not selected. 1 = information area is selected. the information area is mapped into the flash memory address space at addresses fe00h through ffffh . page?page select this 7-bit field selects the flash memory page for programming and page erase operations. flash memory address[15:9] = page[6:0]. flash sector protect register the flash sector protect register ( table 86 ) protects flash memory sectors from being programmed or erased from user code. the fl ash sector protect register shares its register file address with the page select re gister. the flash sector protect register can be accessed only after writing th e flash control register with 5eh . user code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code). sect n ?sector protect 0 = sector n can be programmed or erased from user code. 1 = sector n is protected and cannot be prog rammed or erased from user code. user code can only write bits from 0 to 1. flash frequency high a nd low byte registers the flash frequency high and low byte registers ( table 87 and table 88 ) combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit flash frequency registers must be written with the system clock frequency in khz for program and erase operations. the flash frequency value is calculated using the following equation: flash programming and erasure is not supported for system clock frequen- cies below 20 khz, above 20 mhz, or outside of the valid operating table 86. flash sector protect register (fprot) bits 7 6 5 4 3 2 1 0 field sect7 sect6 sect5 sect4 sect3 sect2 sect1 sect0 reset 0 r/w r/w1 addr ff9h r/w1 = register is accessible for read operations. r egister can be written to 1 only (using user code). ffreq[15:0] ffreqh[ 7:0],ffreql[7:0] {} system clock frequency 1000 ------------------------------------------------------------------ == caution:
ps022517-0508 flash memory z8 encore! xp ? f0822 series product specification 162 frequency range for the device. th e flash frequency high and low byte registers must be loaded with the co rrect value to insure proper program and erase times. ffreqh and ffreql?flash frequency high and low bytes these 2 bytes, {ffreqh[7:0], ffreql[7:0]}, contain the 16-bit flash frequency value. table 87. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 0 r/w r/w addr ffah table 88. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w addr ffbh
ps022517-0508 option bits z8 encore! xp ? f0822 series product specification 163 option bits option bits allow user configuration of certain aspects of z8 encore! xp ? f0822 series operation. the feature configuration data is stored in flash memory and read during reset. features available for control through the option bits are: ? watchdog timer time-out response selection?interrupt or reset. ? watchdog timer enabled at reset. ? the ability to prevent unwa nted read access to user code in flash memory. ? the ability to prevent accident al programming and erasure of all or a portion of the user code in flash memory. ? voltage brownout configuration-always enabled or disabled during stop mode to reduce stop mode power consumption. ? oscillator mode selection-for high, medium, and low power crystal oscillators, or external rc oscillator. operation option bit configuration by reset during any reset operation (system reset, rese t, or stop mode recovery), the option bits are automatically read from the flash memory and written to option configuration registers. the option configuration registers control operation of the devices within the z8 encore! xp f0822 series. option bit cont rol is established before the device exits reset and the ez8 cpu begins code execution. the option configuration registers are not part of the register file and are not accessi ble for read or write access. each time the option bits are programmed or erased, the devi ce must be reset for the change to take place (flash version only) . option bit address space the first two bytes of flash memory at addresses 0000h ( table 89 on page 164) and 0001h ( table 90 on page 165) are reserved for the user programmable option bits. the byte at program memory address 0000h configures user options. the byte at flash mem- ory address 0001h is reserved for future use and must be left in its unprogrammed state.
ps022517-0508 option bits z8 encore! xp ? f0822 series product specification 164 flash memory address 0000h wdt_res?watchdog timer reset 0 = watchdog timer time-out generates an interrupt request. interrupts must be globally enabled for the ez8 cpu to acknowledge the interrupt request. 1 = watchdog timer time-out causes a reset. this setting is the default for unprogrammed (erased) flash. wdt_ao?watchdog timer always on 0 = watchdog timer is automatically enab led upon application of system power. watchdog timer can not be disabled. 1 = watchdog timer is enabled upon executio n of the wdt instruction. once enabled, the watchdog timer can only be disabled by a reset or stop mode recovery. this setting is the de fault for unprogramm ed (erased) flash. osc_sel[1:0]?oscilla tor mode selection 00 = on-chip oscillator configured for use with external rc networks (<4 mhz). 01 = minimum power for use with very low frequency crystals (32 khz to 1.0 mhz). 10 = medium power for use with medium fre quency crystals or ceramic resonators (0.5 mhz to 10.0 mhz). 11 = maximum power for use with high frequ ency crystals (8.0 mhz to 20.0 mhz). this setting is the de fault for unprogramm ed (erased) flash. vbo_ao?voltage brownout protection always on 0 = voltage brownout protection is disabl ed in stop mode to reduce total power consumption. 1 = voltage brownout protection is always enabled including during stop mode. this setting is the defa ult for unprogrammed (erased) flash. rp?read protect 0 = user program code is inaccessible. lim ited control features are available through the ocd. 1 = user program code is accessible. all ocd commands are enabled. this setting is the defa ult for unprogrammed (erased) flash. table 89. option bits at flash memory address 0000h for 8k series flash devices bits 7 6 5 4 3 2 1 0 field wdt_res wdt_ao osc_sel[1:0] vbo_ao rp reserved fwp reset u r/w r/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps022517-0508 option bits z8 encore! xp ? f0822 series product specification 165 reserved these option bits are reserved for future use and must always be 1. the following informatio n applies only to the flash versions of the f0822 series devices: fwp?flash write protect these two option bits combine to provide th ree levels of program memory protection: flash memory address 0001h reserved these option bits are reserved for future use and must always be 1. this setting is the default for unprogram med (erased) flash. fwp description 0 programming, page erase, and mass erase using user code is disabled. mass erase is available through the ocd. 1 programming and page erase are enabled for all of flash program memory. table 90. options bits at flash memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved reset u r/w r/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write.
ps022517-0508 option bits z8 encore! xp ? f0822 series product specification 166
ps022517-0508 on-chip oscillator z8 encore! xp ? f0822 series product specification 167 on-chip oscillator z8 encore! xp ? f0822 series products feature an on-c hip oscillator for use with external crystals with frequencies from 32 khz to 20 mhz. in additio n, the oscillator can support external rc networks with osc illation frequencies up to 4 mhz or ceramic resonators with oscillation frequencies up to 20 mhz. this oscillator genera tes the primary system clock for the internal ez8 cpu and the majority of the on-chip peripherals. alternatively, the x in input pin can also accept a cmos-level cl ock input signal (32 khz?20 mhz). if an external clock genera tor is used, the x out pin must be left unconnected. when configured for use with cr ystal oscillators or external cl ock drivers, the frequency of the signal on the x in input pin determines the frequency of the system clock (that is, no internal clock divider). in rc operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle. operating modes z8 encore! xp f0822 series products support 4 different oscillator modes: ? on-chip oscillator configured for use with external rc networks (<4 mhz). ? minimum power for use with very low fre quency crystals (32 khz to 1.0 mhz). ? medium power for use with medium frequ ency crystals or ceramic resonators (0.5 mhz to 10.0 mhz). ? maximum power for use with high frequency cr ystals or ceramic re sonators (8.0 mhz to 20.0 mhz). the oscillator mode is selected through u ser-programmable option bits. for more infor- mation, see option bits on page 163. crystal oscillator operation figure 34 on page 168 displays a recommended configuration for connection with an external fundamental-mode, pa rallel-resonant crystal opera ting at 20 mhz. recommended 20 mhz crystal specifications are provided in table 91 on page 168. resistor r1 is optional and limits total power dissipation by th e crystal. the printed circuit board layout must add no more than 4 pf of stray capacitance to either the x in or x out pins. if oscilla- tion does not occur, reduce the values of capacitors c1 and c2 to decrease loading.
ps022517-0508 on-chip oscillator z8 encore! xp ? f0822 series product specification 168 figure 34. recommended 20 mhz crystal oscillator configuration oscillator operation with an external rc network the external rc oscillator mode is app licable to timing insen sitive applications. figure 35 on page 169 displays a recommended conf iguration for connectio n with an external resistor-capacitor (rc) network. table 91. recommended crystal oscillator specifications (20 mhz operation) parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s ) 25 w maximum load capacitance (c l )20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 22 pf c1 = 22 pf crystal xout xin on-chip oscillator r1 = 220
ps022517-0508 on-chip oscillator z8 encore! xp ? f0822 series product specification 169 figure 35. connecting the on-chip oscillator to an external rc network an external resistance value of 45 k is recommended for oscillator operation with an external rc network. the minimum resistan ce value to ensure operation is 40 k . the typical oscillator frequency can be esti mated from the values of the resistor ( r in k ) and capacitor ( c in pf) elements using the below equation: figure 36 on page 170 displays the typical (3.3 v and 25 0 c) oscillator frequency as a function of the capacitor ( c in pf) employed in the rc network assuming a 45 k exter- nal resistor. for very small values of c, the parasitic capacitance of the oscillator xin pin and the printed circuit board should be incl uded in the estimation of the oscillator fre- quency. it is possible to operate the rc oscillator usin g only the parasitic ca pacitance of the pack- age and printed circuit board. to minimize sens itivity to external par asites, external capac- itance values in excess of 20 pf are recommended. c x in r v dd oscillator frequency (khz) 1 6 10 0.4 r c () 4c () + ---------------------------------------------------------------- =
ps022517-0508 on-chip oscillator z8 encore! xp ? f0822 series product specification 170 figure 36. typical rc oscillator frequency as a function of the external capacitance with a 45 k resistor when using the external rc oscilla tor mode, the oscillator can stop oscillating if the power supp ly drops below 2.7 v, but before the power sup- ply drops to the voltage brownout th reshold. the oscillator resumes oscil- lation when the supply voltage exceeds 2.7 v. 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 c (pf) frequency (khz) caution:
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 171 on-chip debugger z8 encore! xp ? f0822 series products have an in tegrated on-chip debugger (ocd) that provides advanced debugging features including: ? reading and writing of the register file ? reading and (flash version only) writing of program and data memory ? setting of breakpoints ? executing ez8 cpu instructions architecture the ocd consists of four primary functiona l blocks: transmitter, receiver, autobaud generator, and debug controller. figure 37 displays the architecture of the ocd. figure 37. on-chip debugger block diagram operation ocd interface the ocd uses the dbg pin for communication with an external host. this one-pin interface is a bi-directional open-drain interfa ce that transmits and receives data. data auto-baud system clock transmitter receiver dbg pin debug controller ez8 cpu control detector/generator
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 172 transmission is half-duplex, in that transm it and receive cannot occur simultaneously. the serial data on the dbg pin is sent using the standard asynchronous data format defined in rs-232. this pin can interface the z8 encore! xp f0822 series products to the serial port of a host pc using minimal external hardwa re.two different meth ods for connecting the dbg pin to an rs-232 interface are displayed in figure 38 and figure 39 . for operation of the ocd, all power pins (v dd and av dd ) must be sup- plied with power, and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must always be connected to v dd through an external pull-up resistor to insure proper operation. figure 38. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) figure 39. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) caution: rs-232 tx rs-232 rx rs-232 transceiver v dd dbg pin 10k ohm diode rs-232 tx rs-232 rx rs-232 transceiver v dd dbg pin 10 k open-drain buffer
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 173 debug mode the operating characteristics of the z8 encore! xp ? f0822 series devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez 8 cpu, unless directed by the ocd to execute specific instructions. ? the system clock operates unless in stop mode. ? all enabled on-chip peripherals operate unless in stop mode. ? automatically exits halt mode. ? constantly refreshes the wa tchdog timer, if enabled. entering debug mode the device enters debug mode following any of the following operations: ? writing the dbgmode bit in the ocd control register to 1 using the ocd interface. ? ez8 cpu execution of a brk (breakpoint) instruction. ? match of pc to ocdcntr register (when enabled) ? ocdcntr register decrements to 0000h (when enabled) ? if the dbg pin is low when the device exits reset, the ocd automatically puts the device into debug mode. exiting debug mode the device exits debug mode following any of the following operations: ? clearing the dbgmode bit in the ocd control register to 0. ? power-on reset ? voltage brownout reset ? asserting the reset pin low to initiate a reset. ? driving the dbg pin low while the devi ce is in stop mode initiates a system reset. ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data b its (least-significant bit first), and 1 stop bit (see figure 40 ). figure 40. ocd data format startd0d1d2d3d4d5d6d7stop
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 174 ocd auto-baud detector/generator to run over a range of baud rates (bits per second) with various system clock frequencies, the ocd contains an au to-baud detector/generator. after a reset, the ocd is idle until it receives data. the ocd requires that the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (o ne start bit plus 7 data bits). the auto-baud detector measures this peri od and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocke d by the system clock. the minimum baud rate is the system clock frequency divided by 512. for optimal operation, the maximum recommended baud rate is the system cloc k frequency divided by 8. the theoretical maximum baud rate is the system clock frequ ency divided by 4. this theoretical maxi- mum is possible for low noise designs with clean signals. table 92 lists minimum and recommended maximum baud rates for sample crystal frequencies. if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. the auto-baud dete ctor/generator can then be reconfigured by sending 80h . ocd serial errors the ocd can detect any of the fo llowing error co nditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and ho st simultaneous transmissi on detected by the ocd) when the ocd detects one of these errors, it aborts any command currently in progress, transmits a serial break 4096 system clock cycles long back to the host, and resets the auto-baud detector/generator. a framing er ror or transmit collision can be caused by the host sending a serial break to the ocd. be cause of the open-drain nature of the inter- face, returning a serial break break back to th e host only extends the length of the serial break if the host releases the serial break early. table 92. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) minimum baud rate (kbps) 20.0 2500 39.1 1.0 125.0 1.96 0.032768 (32 khz) 4.096 0.064
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 175 the host transmits a serial break on the dbg pin when first connecting to the z8 encore! xp ? f0822 series device or when recove ring from an error. a serial break from the host resets the auto-baud generator/detector but does not reset the ocd con- trol register. a serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial break when the dbg pin returns high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. breakpoints execution breakpoints are generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signal s the ocd. if breakpoints are enabled, the ocd idles the ez8 cpu and enters debug mo de. if breakpoints are not enabled, the ocd ignores the brk signal and the brk inst ruction operates as an nop instruction. if breakpoints are enabled, the ocd can be configured to automa tically enter debug mode, or to loop on the break instruction. if the ocd is configured to loop on the brk instruction, then th e cpu is still enabled to servic e dma and interrupt requests. the loop on brk instruction can be used to service interrupts in the background. for interrupts to be serviced in the background, there cannot be any breakpoints in the isr. otherwise, the cpu stops on the breakpoint in the interrupt routine. for interrupts to be serviced in the background, interrupts must al so be enabled. debugging software should not automatically enable interru pts when using this feature, since interrupts are typically disabled during critical sections of code wher e interrupts should not occur (such as adjust- ing the stack pointer or modifying shared data). software can poll the idle bit of the ocdstat register to determine if the ocd is loop- ing on a brk instruction. when software want s to stop the cpu on the brk instruction it is looping on, software shou ld not set the dbgmode bit of the ocdctl register. the cpu can have vectored to and be in the middle of an isr when this bit gets set. instead, software must clear the brklp bit. this allo ws the cpu to finish the isr it is in and return the brk instruction. when the cpu re turns to the brk instruction it was previ- ously looping on, it automatically sets the dbgmode bit and enter debug mode. software should also note that the majority of the ocd commands are still disabled when the ez8 cpu is looping on a brk instruction. the ez8 cpu must be stopped and the part must be in debug mode before these commands can be issued. breakpoints in flash memory the brk instruc tion is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the desired address, over- writing the current instruction. to remove a breakpoint, the correspon ding page of flash memory must be erased and reprogrammed with the original data.
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 176 ocdcntr register the ocd contains a multipurpose 16-bit coun ter register. it can be used for the following: ? count system clock cycles between breakpoints. ? generate a brk when it counts down to zero. ? generate a brk when its valu e matches the program counter. when configured as a counter, the ocdcntr register starts counting when the ocd leaves debug mode and stops counting when it enters debug mode again or when it reaches the maximum count of ffffh . the ocdcntr register automatically resets itself to 0000h when the ocd exits debug mode if it is configured to count clock cycles between breakpoints. the ocdcntr register is used by many of the ocd commands. it counts the number of bytes for the register and memory read/write commands. it holds the residual value when genera ting the crc. therefore, if the ocd- cntr is being used to generate a brk, its value should be written as a last step before leaving debug mode. since this register is overwritten by variou s ocd commands, it shou ld only be used to generate temporary breakpoints, such as steppi ng over call instructio ns or running to a specific instruction and stopping. on-chip debugger commands the host communicates to th e ocd by sending ocd commands using the dbg interface. during normal operation, only a subset of the ocd commands are available. in debug mode, all ocd commands become available unl ess the user code and control registers are protected by programming the read protect option bit ( rp ). the read protect option bit prevents the code in memory from being read out of the z8 encore! xp f0822 series products. when this option is enabled, se veral of the ocd commands are disabled. table 93 on page 177 contains a summary of the ocd commands. each ocd command is described further in the bullete d list. it also lists the comm ands that operate when the device is not in debug mode (normal operation) and those commands that are disabled by programming the read protect option bit. caution:
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 177 table 93. on-chip debugger commands debug command command byte enabled when not in debug mode? disabled by read protect option bit read ocd revision 00h yes - write ocd counter register 01h - - read ocd status register 02h yes - read ocd counter register 03h - - write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes - write program counter 06h - disabled read program counter 07h - disabled write register 08h - only writes of the peripheral control registers at address f00h-ffh are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h - only reads of the peripheral control registers at address f00h-ffh are allowed. write program memory 0ah - disabled read program memory 0bh - disabled write data memory 0ch - disabled read data memory 0dh - disabled read program memory crc 0eh - - reserved 0fh - - step instruction 10h - disabled stuff instruction 11h - disabled
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 178 in the following bulleted list of ocd commands, data and commands sent from the host to the ocd are identified by ? dbg command/data ?. data sent from the ocd back to the host is identified by ? dbg data ? ? read ocd revision (00h) ?the read ocd revision command determines the version of the ocd. if ocd commands are added, removed, or changed, this revision number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) ? write ocd counter register (01h) ?the write ocd counter register command writes the data that follows to the ocdcnt r register. if the device is not in debug mode, the data is discarded. dbg 01h dbg ocdcntr[15:8] dbg ocdcntr[7:0] ? read ocd status register (02h) ?the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] ? read ocd counter register (03h) ?the ocd counter register can be used to count system clock cycles in between brea kpoints, generate a brk when it counts down to zero, or generate a brk when its value matches the program counter. since this register is really a down counter, the re turned value is inverted when this register is read so the returned result appears to be an up counter. if th e device is not in debug mode, this command returns ffffh. dbg 03h dbg ~ocdcntr[15:8] dbg ~ocdcntr[7:0] ? write ocd control register (04h) ?the write ocd control register command writes the data that follows to the ocdctl register. when the read protect option bit is enabled, the dbgmode bit (ocdctl[7]) can only be set to 1, it cannot be cleared to 0 and the only method of puttin g the device back into normal operating mode is to reset the device. execute instruction 12h - disabled reserved 13h - ffh - - table 93. on-chip debugger commands (continued) debug command command byte enabled when not in debug mode? disabled by read protect option bit
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 179 dbg 04h dbg ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. dbg 05h dbg ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s program counter. if the device is not in debug mode or if the read protect option bit is enabled, the program counter values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0] ? read program counter (07h) ?the read program coun ter command reads the value in the ez8 cpu?s program counter. if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] ? write register (08h) ?the write register command writ es data to the register file. data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). if the device is not in debug mode , the address and data values are discarded. if the read protect option bit is enabled, then only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? read register (09h) ?the read register command reads data from the register file. data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). reading peripheral control registers through the ocd does not effect peripheral operation. for example, register bits that are normally cleared upon a read operation will not be effected (wdtstat register is affected by ocd read register operation). if the device is not in debug mode or if th e read protect option bit is enabled, this command returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 180 ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equiva lent to the ldc and ldci instructions. data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). the on-chip flash controller mu st be written to and unlocked for the programming operation to occur. if the flas h controller is not unlocked, the data is discarded. if the device is not in debug mo de or if the read protect option bit is enabled, the data is discarded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory (0bh) ?the read program memory command reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). if the device is not in debug mode or if the read protect option bit is enabled, this command returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? (flash version only) wr ite data memory (0ch) ?the write data memory command writes data to data memory. this command is equivale nt to the lde and ldei instructions. data can be written 1-6 5536 bytes at a time (65536 bytes can be written by setting size to 0). if the device is not in debug mode or if the read protect option bit is enabled, the data is discarded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read data memory (0dh) ?the read data memory command reads from data memory. this command is equivalent to th e lde and ldei instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8]
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 181 dbg size[7:0] dbg 1-65536 data bytes ? read program memory crc (0eh) ?the read program memory crc command computes and returns the crc (cyclic redu ndancy check) of program memory using the 16-bit crc-ccitt polynomial. if the de vice is not in debug mode, this command returns ffffh for the crc value. unlike most other ocd read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and returns the result. the delay is a function of the progra m memory size and is approximately equal to the system clock period multiplied by th e number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0] ? step instruction (10h) ?the step instruction co mmand steps one assembly instruction at the current program counter location. if the device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly instruction and allows specification of the fi rst byte of the instruction. the remaining 0-4 bytes of the instruction are read from program memory. this command is useful for stepping over instructions where the first byte of the in struction has been overwritten by a breakpoint. if the device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg 11h dbg opcode[7:0] ? execute instruction (12h) ?the execute instruction co mmand allows sending an entire instruction to be executed to the ez 8 cpu. this command can also step over breakpoints. the number of bytes to send for the instruction depends on the opcode. if the device is not in debug mode or the re ad protect option bit is enabled, the ocd ignores this command dbg 12h dbg 1-5 byte opcode on-chip debugger control register definitions ocd control register the ocd control register controls the state of the ocd. this register enters or exits debug mode and enables the brk instructio n. it can also reset the z8 encore! xp ? f0822 series device.
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 182 a ?reset and stop? function can be achieved by writing 81h to this register. a ?reset and go? function can be achieved by writing 41h to this register. if the device is in debug mode, a ?run? function can be implemented by writing 40h to this register. dbgmode?debug mode setting this bit to 1 causes the device to en ter debug mode. when in debug mode, the ez8 cpu stops fetching new instructions. clea ring this bit causes the ez8 cpu to start running again. this bit is au tomatically set when a brk inst ruction is decoded and break- points are enabled. if the read protect option bit is enabled, this bit can only be cleared by resetting the device, it cannot be written to 0. 0 = the z8 encore! xp f0822 series de vice is operating in normal mode. 1 = the z8 encore! xp f0822 se ries device is in debug mode. brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, break- points are disabled and the brk instruction beha ves like an nop instruction. if this bit is set to 1 and a brk instruction is decoded, the ocd takes action de pendent upon the brk- loop bit. 0 = brk instruction is disabled. 1 = brk instruction is enabled. dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, then the ocd sends an debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. brkloop?breakpoint loop this bit determines what ac tion the ocd takes when a brk instruction is decoded if breakpoints are enabled (brken is 1). if this bit is 0, then the dbgmode bit is automat- ically set to 1 and the ocd enter debug mo de. if brkloop is set to 1, then the ez8 cpu loops on the brk instruction. 0 = brk instruction sets dbgmode to 1. 1 = ez8 cpu loops on brk instruction. brkpc?break when pc == ocdcntr if this bit is set to 1, then the ocdcntr regi ster is used as a hardware breakpoint. when the program counter matches the value in the ocdcntr register, dbgmode is table 94. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack brkloo p brkpc brkzro reserved rst reset 0 r/w r/w r r/w
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 183 automatically set to 1. if this bit is set, the ocdcntr register does not count when the cpu is running. 0 = ocdcntr is setup as counter 1 = ocdcntr generates hardware break when pc == ocdcntr brkzro?break when ocdcntr == 0000h if this bit is set, then the ocd automatically sets the dbgmode bit when the ocd- cntr register counts down to 0000h . if this bit is set, the ocdcntr register is not reset when the part leaves debug mode. 0 = ocd does not generate brk when ocdcntr decrements to 0000h 1 = ocd sets dbgmode to 1 when ocdcntr decrements to 0000h reserved these bits are reserved and must be 0. rst?reset setting this bit to 1 resets the z8 encore! xp ? f0822 series device. the device goes through a normal por sequence with the except ion that the ocd is not reset. this bit is automatically cleared to 0 when the reset finishes. 0 = no effect. 1 = reset the z8 encore! xp f0822 series device. ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. idle?cpu idling this bit is set if the part is in debug mo de (dbgmode is 1), or if a brk instruction occurred since the last time oc dctl was written. this can be used to determine if the cpu is running or if it is idling. 0 = the ez8 cpu is running. 1 = the ez8 cpu is either stopped or looping on a brk instruction. halt?halt mode 0 = the device is not in halt mode. 1 = the device is in halt mode. table 95. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field idle halt rpen reserved reset 0 r/w r
ps022517-0508 on-chip debugger z8 encore! xp ? f0822 series product specification 184 rpen?read protect option bit enabled 0 = the read protect option bit is disabled (1). 1 = the read protect option bit is enab led (0), disabling many ocd commands. reserved. must be 0
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 185 electrical characteristics absolute maximum ratings stresses greater than those listed in table 96 can cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating conditio ns for extended periods can affect device reliability. for improved reliability, unused inputs must be tied to one of the supply voltages (v dd or v ss ). table 96. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +105 c 1 storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v 2 voltage on av ss pin with respect to v ss ?0.3 +0.3 v 2 voltage on v dd pin with respect to v ss ?0.3 +3.6 v voltage on av dd pin with respect to v dd ?0.3 +0.3 v maximum current on input and/or inactive output pin ?5 +5 a maximum output curr ent from active output pin -25 +25 ma 20-pin ssop package maximum ratings at -40 c to 70 c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma 20-pin ssop package maximum ratings at 70 c to 105 c total power dissipation 250 mw maximum current into v dd or out of v ss 69 ma 20-pin pdip package maximum ratings at -40 c to 70 c total power dissipation 775 mw maximum current into v dd or out of v ss 215 ma caution:
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 186 20-pin pdip package maximum ratings at 70 c to 105 c total power dissipation 285 mw maximum current into v dd or out of v ss 79 ma 28-pin soic package maximum ratings at -40 c to 70 c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma 28-pin soic package maximum ratings at 70 c to 105 c total power dissipation 260 mw maximum current into v dd or out of v ss 73 ma 28-pin pdip package maximum ratings at -40 c to 70 c total power dissipation 1100 mw maximum current into v dd or out of v ss 305 ma 28-pin pdip package maximum ratings at 70 c to 105 c total power dissipation 400 mw maximum current into v dd or out of v ss 110 ma note: this voltage applies to all pins except the following: vdd, avdd, vref, pins supporting analog input (port b), and where noted otherwise. table 96. absolute maximum ratings (continued) parameter minimum maximum units notes
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 187 dc characteristics table 97 lists the dc characteris tics of the z8 encore! xp ? f0822 series products. all voltages are referenced to v ss , the primary system ground. table 97. dc characteristics symbol parameter t a = -40 c to 105 c units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v for all input pins except reset , dbg, and xin. v il2 low level input voltage -0.3 ? 0.2*v dd vfor reset , dbg, and xin. v ih1 high level input voltage 0.7*v dd ? 5.5 v ports a and c pins when their programmable pull-ups are disabled. v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v port b pins. ports a and c pins when their programmable pull- ups are enabled. v ih3 high level input voltage 0.8*v dd ?v dd +0.3 v reset , dbg, and xin pins. v ol1 low level output voltage ??0.4vi ol = 2 ma; vdd = 3.0 v high output drive disabled. v oh1 high level output voltage 2.4 ? ? v i oh = -2 ma; vdd = 3.0 v high output drive disabled. v ol2 low level output voltage high drive ??0.6vi ol = 20 ma; vdd = 3.3 v high output drive enabled t a = -40 c to +70 c v oh2 high level output voltage high drive 2.4 ? ? v i oh = -20 ma; vdd = 3.3 v high output drive enabled; t a = -40 c to +70 c v ol3 low level output voltage high drive ??0.6vi ol = 15ma; vdd = 3.3 v high output drive enabled; t a = +70 c to +105 c v oh3 high level output voltage high drive 2.4 ? ? v i oh = 15 ma; vdd = 3.3 v high output drive enabled; t a = +70 c to +105 c
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 188 figure 41 on page 189 displays the typical active mode current consumption while operat- ing at 25 oc, 3.3 v, versus the system cloc k frequency. all gpio pins are configured as outputs and driven high. v ram ram data retention 0.7 ? ? v i il input leakage current -5 ? +5 av dd = 3.6 v; v in = vdd or vss 1 i tl tri-state leakage current -5 ? +5 av dd = 3.6 v c pad gpio port pad capacitance ?8.0 2 ?pf c xin xin pad capacitance ?8.0 2 ?pf c xout xout pad capacitance ?9.5 2 ?pf i pu1 weak pull-up current 92050 a vdd = 2.7?3.6 v. t a = 0 c to +70 c i pu2 weak pull-up current 72075 a vdd = 2.7?3.6 v. t a = -40 c to +105 c 1 this condition excludes all pins that have on-chip pull-ups, when driven low. 2 these values are provided for design guidance only and are not tested in production. table 97. dc characteristics (continued) symbol parameter t a = -40 c to 105 c units conditions minimum typical maximum
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 189 figure 41. typical active mode i dd versus system clock frequency figure 42 displays the maximum active mode curre nt consumption across the full operat- ing temperature range of the device and versus the system clock frequency. all gpio pins are configured as outputs and driven high. figure 42. maximum active mode i dd versus system clock frequency 0 2.5 5 7.5 10 12.5 15 0 5 10 15 20 system clock frequency (mhz) idd (ma) 2.7v 3.0v 3.3v 3.6v 0 2.5 5 7.5 10 12.5 15 05101520 system clock frequency (mhz) idd (ma) 2.7v 3.0v 3.3v 3.6v
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 190 figure 43 displays the typical current consump tion in halt mode wh ile operating at 25 oc versus the system clock frequency. a ll gpio pins are configured as outputs and driven high. figure 43. typical halt mode i dd versus system clock frequency 0.000 1.000 2.000 3.000 4.000 5.000 0 5 10 15 20 system clock frequency (mhz) idd (ma ) 2.7v 3.0v 3.3v 3.6v
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 191 figure 44 displays the maximum halt mode current consumption across the full operating temperature range of the device and versus the system clock frequency. all gpio pins are configured as outputs and driven high. figure 44. maximum halt mode i cc versus system clock frequency 0.000 1.000 2.000 3.000 4.000 5.000 0 5 10 15 20 system clock frequency (mhz) idd (ma ) 2.7v 3.0v 3.3v 3.6v
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 192 figure 45 displays the maximum current consump tion in stop mode with the vbo and watchdog timer enabled versus the power supp ly voltage. all gpio pins are configured as outputs and driven high. figure 45. maximum stop mode i dd with vbo enabled versus power supply voltage figure 46 on page 193 displays the maximum current consumption in stop mode with the vbo disabled and watchdog timer enabled versus the power supply voltage. all gpio pins are configured as outputs and driven high. disabling the watchdog timer and its internal rc oscillator in stop mode will provide some additional reduction in stop mode current consumption. this small current reduction is indistinquishable on the scale of figure 46 on page 193. 400 450 500 550 600 650 2.733.33.6 vdd (v) idd (ua) 25c 0/70c -40/105c l
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 193 figure 46. maximum stop mode i dd with vbo disabled versus power supply voltage 0 50 100 150 200 2.7 3 3.3 3.6 vdd (v) idd (ua) -40/105c 0/70c 25c
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 194 ac characteristics table 98 provides information on the ac characte ristics and timing. all ac timing infor- mation assumes a standard load of 50 pf on all outputs. table 98. ac characteristics symbol parameter v dd = 2.7 - 3.6 v t a = -40 c to 105 c units conditions minimum maximum f sysclk system clock frequency (rom) ?20.0mhz f sysclk system clock frequency (flash) ? 20.0 mhz read-only from flash memory. 0.032768 20.0 mhz program or erasure of the flash memory. f xtal crystal oscillator frequency 0.032768 20.0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver. t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50 ns t xinl system clock low time 20 30 ns t clk = 50 ns
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 195 on-chip peripheral ac and dc electrical characteristics table 99 provides information on the power-on reset and voltage brownout electrical characteristics. table 99. power-on reset and voltage brownout electrical characteristics and timing symbol parameter t a = -40 c to 105 c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.15 2.40 2.60 v v dd = v por v vbo voltage brownout reset voltage threshold 2.05 2.30 2.55 v v dd = v vbo v por to v vbo hysteresis 50 100 ? mv starting v dd voltage to ensure valid por ?v ss ?v t ana por analog delay ? 50 ? sv dd > v por ; t por digital reset delay follows t ana t por por digital delay ? 5.0 ? ms 50 wdt oscillator cycles (10 khz) + 16 system clock cycles (20 mhz) t vbo voltage brownout pulse rejection period ?10 ? sv dd < v vbo to generate a reset. t ramp time for vdd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms 1 data in the typical column is from characterization at 3. 3 v and 25 c. these values are provided for design guidance only and are not tested in production.
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 196 table 100 provides information on the external rc oscillator electrical characteristics and timing, and table 101 provides information on the flash memory electrical characteris- tics and timing. table 100. external rc oscillator electrical characteristics and timing symbol parameter t a = -40 c to 105 c units conditions minimum typical 1 maximum v dd operating voltage range 2.70 1 ??v r ext external resistance from xin to vdd 40 45 200 k c ext external capacitance from xin to vss 0201000pf f osc external rc oscillation frequency ??4mhz 1 when using the external rc oscillator mode, the oscillator can stop oscillat ing if the power supply drops below 2.7 v, but before the power supply drops to the voltage brown-out threshold. the oscillator will resume oscillation as soon as the supply voltage exceeds 2.7 v. table 101. flash memory electrical characteristics and timing parameter v dd = 2.7 - 3.6v t a = -40 c to 105 c units notes minimum typical maximum flash byte read time 50 ? ? s flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ?? 2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller.
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 197 table 102 provides information on the reset a nd stop mode recovery pin timing and table 103 provides information on the watchdog timer electrical characteristics and timing. data retention 100 ? ? years 25 c endurance 10,000 ? ? cycles program / erase cycles table 102. reset and stop mode recovery pin timing symbol parameter t a = -40 c to 105 c units conditions minimum typical maximum t reset reset pin assertion to initiate a system reset 4??t clk not in stop mode. t clk = system clock period. t smr stop mode recovery pin pulse rejection period 10 20 40 ns reset , dbg and gpio pins configured as smr sources. 1 when using the external rc oscillator mode, the oscill ator can stop oscillating if the power supply drops below 2.7 v, but before the power supply drops to the voltage brown-out threshold. the oscillator will resume oscillation as soon as the supply voltage exceeds 2.7 v. table 103. watchdog timer electrical characteristics and timing symbol parameter v dd = 2.7?3.6 v t a = -40 c to 105 c units conditions minimum typical maximum f wdt wdt oscillator frequency 5 10 20 khz i wdt wdt oscillator current including internal rc oscillator ?< 15 a table 101. flash memory electrical characteristics and timing (continued) parameter v dd = 2.7 - 3.6v t a = -40 c to 105 c units notes minimum typical maximum
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 198 figure 47 displays the input frequen cy response of the adc. figure 47. analog-to-digital converter frequency response frequency (khz) 0.9 0.8 0.7 0.6 0.3 0.4 0.2 0.1 0 frequency response 1 0.5 0 5 10 15 20 25 30 -6 db -3 db adc magnitude transfer function (linear scale)
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 199 table 104. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0?3.6 v t a = -40 c to 105 c units conditions minimum typical maximum resolution 10 ? ? bits external v ref = 3.0 v; differential nonlinearity (dnl) -0.25 ? 0.25 lsb guaranteed by design integral nonlinearity (inl) -2.0 ? 2.0 lsb external v ref = 3.0 v dc offset error -35 ? 25 mv v ref internal refe rence voltage 1.9 2.0 2.4 v v dd = 3.0 - 3.6 v t a = -40 c to 105 c vc ref voltage coefficient of internal refe rence voltage ?78 ?mv/vv ref variation as a function of avdd. tc ref temperature coefficient of internal refe rence voltage ?1 ?mv/ 0 c single-shot conversion period 5129 cycles system clock cycles continuous conversion period 256 cycles system clock cycles r s analog source impedance ? ? 150 w recommended zin input impedance 150 k v ref external reference voltage avdd v avdd <= vdd. when using an external reference voltage, decoupling capacitance should be placed from vref to avss. i ref current draw into vref pin when driving with external source. 25.0 40.0 a
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 200 general purpose i/o port input data sample timing figure 48 displays timing of the gpio port input sampling. table 105 lists the gpio port input timing. figure 48. port input sample timing table 105. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to xin fall setup time (not pictured) 5? t h_port xin fall to port input transition hold time (not pictured) 5? t smr gpio port pin pulse width to insure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk gpio pin port value changes to 0 0 latched into port input input value gpio input data latch clock data register gpio data read on data bus gpio data register value 0 read by ez8 cpu
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 201 general purpose i/o port output timing figure 49 and table 106 provide timing information for gpio port pins. figure 49. gpio port output timing table 106. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 202 on-chip debugger timing figure 50 and table 107 provide timing information for the dbg pin. the dbg pin timing specifications assume a 4 s maximum rise and fall time. figure 50. on-chip debugger timing table 107. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 10 ? t 4 dbg to xin rise input hold time 5 ? dbg frequency system clock/4 xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 203 spi master mode timing figure 51 and table 108 provide timing information for spi master mode pins. timing is shown with sck rising edge used to sour ce mosi output data, sck falling edge used to sample miso input data. timing on the ss output pin(s) is controlled by software. figure 51. spi master mode timing table 108. spi master mode timing parameter abbreviation delay (ns) minimum maximum spi master t 1 sck rise to mosi output valid delay -5 +5 t 2 miso input to sck (receive edge) setup time 20 t 3 miso input to sck (receive edge) hold time 0 sck mosi t1 (output) miso t2 t3 (input) output data input data
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 204 spi slave mode timing figure 52 and table 109 provide timing information fo r the spi slave mode pins. timing is shown with sck rising edge used to source miso output data, sck falling edge used to sample mosi input data. figure 52. spi slave mode timing table 109. spi slave mode timing parameter abbreviation delay (ns) minimum maximum spi slave t 1 sck (transmit edge) to miso output valid delay 2 * xin period 3 * xin period + 20 nsec t 2 mosi input to sck (receive edge) setup time 0 t 3 mosi input to sck (receive edge) hold time 3 * xin period t 4 ss input assertion to sc k setup 1 * xin period sck miso t1 (output) mosi t2 t3 (input) output data input data ss (input) t4
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 205 i 2 c timing figure 53 and table 110 provide timing information for i 2 c pins. figure 53. i 2 c timing table 110. i 2 c timing parameter abbreviation delay (ns) minimum maximum i 2 c t 1 scl fall to sda output delay scl period/4 t 2 sda input to scl rising edge setup time 0 t 3 sda input to scl falling edge hold time 0 scl sda t1 (output) sda t2 (input) output data input data (output) t3
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 206 uart timing figure 54 and table 111 provide timing information for uart pins for the case where the clear to send input pin (cts ) is used for flow control. in this example, it is assumed that the driver enable polarity has been configured to be active low and is represented here by de . the cts to de assertion delay (t1) assumes the uart transmit data register has been loaded with data prior to cts assertion. figure 54. uart timing with cts table 111. uart timing with cts parameter abbreviation delay (ns) minimum maximum t 1 cts fall to de assertion delay 2 * xin period 2 * xin period + 1 bit period t 2 de assertion to txd falling edge (start) delay 1 bit period 1 bit period + 1 * xin period t 3 end of stop bit(s) to de deassertion delay 1 * xin period 2 * xin period t 1 t 2 txd (output) de (output) cts (input) start bit 0 t 3 bit 7 parity stop bit 1 end of stop bit(s)
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 207 figure 55 and table 112 provide timing information for ua rt pins for the case where the clear to send input signal (cts ) is not used for flow contro l. in this example, it is assumed that the driver enable polarity ha s been configured to be active low and is represented here by de . de asserts after the uart transmit data register has been writ- ten. de remains asserted for multiple characters as long as the transmit data register is written with the next character before the current character has completed. figure 55. uart timing without cts table 112. uart timing without cts parameter abbreviation delay (ns) minimum maximum t 1 de assertion to txd falling edge (start) delay 1 bit period 1 bit period + 1 * xin period t 2 end of stop bit(s) to de deassertion delay 1 * xin period 2 * xin period t 1 txd (output) de (output) start bit 0 t 2 bit 7 parity stop bit 1 end of stop bit(s)
ps022517-0508 electrical characteristics z8 encore! xp ? f0822 series product specification 208
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 209 ez8 cpu instruction set assembly language pro gramming introduction the ez8 cpu assembly language provides a me ans for writing an application program without having to be concerned with actua l memory addresses or machine instruction formats. a program written in assembly langua ge is called a source program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to re present the instructio ns themselves. the opcodes identify the in struction while the operands represe nt memory locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called statements. each statement can contain la bels, operations, oper ands and comments. labels can be assigned to a particular instru ction step in a source program. the label iden- tifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine language program called the obje ct code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, 01h ; another load (ld) instruction with two operands. ; the first operand, extended mode register address 234h , ; is the destination. the sec ond operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h .
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 210 assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination? , but ordering is opcode-dependent. the fol- lowing instruction examples illust rate the format of some ba sic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. example 1 : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: example 2 : in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if th e contents of register 43h and working register r8 are added and the result is stor ed in 43h, the assembl y syntax and resulting object code is: see the device-specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is described in table 115 on page 211. table 113. assembly language syntax example 1 assembly language code add 43h 08h (add dst, src) object code 04 08 43 (opc src, dst) table 114. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 211 . table 115. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see condition codes overview in the ez8 cpu user manual. da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. represents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0 ?15 ir indirect register @reg reg. represent s a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15 r register reg reg. represents a number in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to ? 128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represents a number in the range of 00h to ffh x indexed #index the register or register pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 212 table 116 contains additional symbols that are us ed throughout the instruction summary and instruction set description sections. assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is added to the destin ation data and the result is stored in the des- tination location. table 116. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 213 condition codes the c, z, s, and v flags control the operatio n of the conditional jump (jp cc and jr cc) instructions. sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which forms bits 7:4 of the conditional jump instructions. the condition codes are summarized in table 117 . some binary condition codes can be created using more than one a ssembly code mnemonic. the result of the flag test operation decides if the conditional jump is executed. table 117. condition codes binary hex assembly mnemonic definition flag test operation 0000 0 f always false ? 0001 1 lt less than (s xor v) = 1 0010 2 le less than or equal (z or (s xor v)) = 1 0011 3 ule unsigned less than or equal (c or z) = 1 0100 4 ov overflow v = 1 0101 5 ml minus s = 1 0110 6 z zero z = 1 0110 6 eq equal z = 1 0111 7 c carry c = 1 0111 7 ult unsigned less than c = 1 1000 8 t (or blank) always true ? 1001 9 ge greater than or equal (s xor v) = 0 1010 a gt greater than (z or (s xor v)) = 0 1011 b ugt unsigned greater than (c = 0 and z = 0) = 1 1100 c nov no overflow v = 0 1101 d pl plus s = 0 1110 e nz non-zero z = 0 1110 e ne not equal z = 0 1111 f nc no carry c = 0 1111 f uge unsigned greater than or equal c = 0
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 214 ez8 cpu instruction classes ez8 cpu instructions are divided func tionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift tables 118 through table 125 on page 218 contain the inst ructions belonging to each group and the number of operands required fo r each instruction. some instructions appear in more than one table as these instruction ca n be considered as a subset of more than one category. within these tables, the source oper and is identified as ?src?, the destination operand is ?dst? and a condition code is ?cc?. table 118. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 215 sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract us ing extended addressing table 119. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 120. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto- increment addresses ldei dst, src load external data to/from data memory and auto- increment addresses table 118. arithmetic instructions (continued) mnemonic operands instruction
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 216 table 121. cpu control instructions mnemonic operands instruction ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set register pointer stop ? stop mode wdt ? watchdog timer refresh table 122. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto-increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto-increment addresses ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 217 table 123. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 124. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non- zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 218 ez8 cpu instruction summary table 126 summarizes the ez8 cpu instructions . the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . table 125. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 126. ez8 cpu instruction summary assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 * * * * 0 * 2 3 rir 13 2 4 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 * * * * 0 * 4 3 er im 19 4 3
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 219 add dst, src dst dst + src r r 02 * * * * 0 * 2 3 rir 03 2 4 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 * * * * 0 * 4 3 er im 09 4 3 and dst, src dst dst and src r r 52 - * * 0 - - 2 3 rir 53 2 4 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 - * * 0 - - 4 3 er im 59 4 3 bclr bit, dst dst[bit] 0 r e2 ------ 2 2 bit p, bit, dst dst[bit] p r e2 ------ 2 2 brk debugger break 00 - - - - - - 1 1 bset bit, dst dst[bit] 1 r e2 ------ 2 2 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 - - 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ------ 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ------ 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ------ 3 3 ir f7 3 4 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 220 call dst sp sp -2 @sp pc pc dst irr d4 ------ 2 6 da d6 3 3 ccf c ~c ef *----- 1 2 clr dst dst 00h r b0 ------ 2 2 ir b1 2 3 com dst dst ~dst r 60 - * * 0 - - 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * - - 2 3 rir a3 2 4 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * - - 3 3 rir 1f a3 3 4 rr 1f a4 4 3 rir 1f a5 4 4 rim 1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * - - 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * - - 4 3 er im a9 4 3 da dst dst da(dst) r 40 * * * x - - 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 - * * * - - 2 2 ir 31 2 3 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 221 decw dst dst dst - 1 rr 80 - * * * - - 2 5 irr 81 2 6 di irqctl[7] 0 8f ------ 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ------ 2 3 ei irqctl[7] 1 9f ------ 1 2 halt halt mode 7f ------ 1 2 inc dst dst dst + 1 r 20 - * * * - - 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 - * * * - - 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ****** 1 5 jp dst pc dst da 8d ------ 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ------ 3 2 jr dst pc pc + x da 8b ------ 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ------ 2 2 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 222 ld dst, rc dst src r im 0c-fc ------ 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 2 3 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 ldc dst, src dst src r irr c2 ------ 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 - - - - - - 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ------ 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 - - - - - - 2 9 irr ir 93 2 9 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 223 ldx dst, src dst src r er 84 ------ 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ------ 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ------ 2 8 nop no operation 0f - - - - - - 1 2 or dst, src dst dst or src r r 42 - * * 0 - - 2 3 rir 43 2 4 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 - * * 0 - - 4 3 er im 49 4 3 pop dst dst @sp sp sp + 1 r 50 ------ 2 2 ir 51 2 3 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 224 popx dst dst @sp sp sp + 1 er d8 ------ 3 2 push src sp sp ? 1 @sp src r 70 ------ 2 2 ir 71 2 3 pushx src sp sp ? 1 @sp src er c8 ------ 3 2 rcf c 0 cf 0----- 1 2 ret pc @sp sp sp + 2 af ------ 1 4 rl dst r 90 * * * * - - 2 2 ir 91 2 3 rlc dst r 10 * * * * - - 2 2 ir 11 2 3 rr dst r e0 ****-- 2 2 ir e1 2 3 rrc dst r c0 * * * * - - 2 2 ir c1 2 3 sbc dst, src dst dst ? src - c r r 32 * * * * 1 * 2 3 rir 33 2 4 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 * * * * 1 * 4 3 er im 39 4 3 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h d7 d6 d5 d4 d3 d2 d1 d0 dst d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 225 scf c 1 df 1----- 1 2 sra dst r d0 * * * 0 - - 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * - - 3 2 ir 1f c1 3 3 srp src rp src im 01 ------ 2 2 stop stop mode 6f ------ 1 2 sub dst, src dst dst ? src r r 22 * * * * 1 * 2 3 rir 23 2 4 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst dst ? src er er 28 * * * * 1 * 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x - - 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 - * * 0 - - 2 3 rir 63 2 4 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 - * * 0 - - 4 3 er im 69 4 3 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h d7 d6 d5 d4 d3 d2 d1 d0 dst d7 d6 d5 d4 d3 d2 d1 d0 dst
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 226 tm dst, src dst and src r r 72 - * * 0 - - 2 3 rir 73 2 4 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 - * * 0 - - 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ------ 2 6 wdt 5f ------ 1 2 xor dst, src dst dst xor src r r b2 - * * 0 - - 2 3 rir b3 2 4 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 - * * 0 - - 4 3 er im b9 4 3 flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1 table 126. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 227 flags register the flags register contains the status inform ation regarding the most recent arithmetic, logical, bit manipulation or rotate and shift oper ation. the flags register contains six bits of status information that are set or cleared by cpu operations. four of the bits (c, v, z and s) can be tested with conditional jump in structions. two flags (h and d) cannot be tested and are used for binary -coded decimal (bcd) arithmetic. the two remaining bits, user flags (f1 and f2 ), are available as general-purpose status bits. user flags are unaffected by arithmetic operations and must be set or cleared by instructions. the user flags cannot be used with conditional jumps. they are undefined at initial power-up and are unaffected by reset. figure 56 illustrates the flags and their bit positions in the flags register. figure 56. flags register interrupts, the software trap (trap) instruction, and illegal instruction traps all write the value of the flags register to the stack. executing an interrupt return (iret) instruc- tion restores the value saved on th e stack into the flags register. c z s v d h f2 f1 flags register bit 0 bit 7 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag user flags
ps022517-0508 ez8 cpu instruction set z8 encore! xp ? f0822 series product specification 228
ps022517-0508 opcode maps z8 encore! xp ? f0822 series product specification 229 opcode maps a description of the opcode map data and the abbreviations are provided in figure 57 and table 127 on page 230. figure 58 on page 231 and figure 59 on page 232 provide infor- mation on each of the ez8 cpu instructions. figure 57. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps022517-0508 opcode maps z8 encore! xp ? f0822 series product specification 230 table 127. opcode map abbreviations abbreviation description abbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps022517-0508 opcode maps z8 encore! xp ? f0822 series product specification 231 figure 58. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.2 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map
ps022517-0508 opcode maps z8 encore! xp ? f0822 series product specification 232 figure 59. second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex)
ps022517-0508 packaging z8 encore! xp ? f0822 series product specification 233 packaging figure 60 displays the 20-pin ssop package available for z8 encore! xp ? f0822 series devices. figure 60. 20-pin small shrink outline package (ssop) figure 61 displays the 20-pin pdip package available for z8 encore! xp f0822 series devices. figure 61. 20-pin plastic dual-inline package (pdip)
ps022517-0508 packaging z8 encore! xp ? f0822 series product specification 234 figure 62 displays the 28-pin soic package av ailable for z8 enco re! xp f0822 series devices. figure 62. 28-pin small outline integrated circuit package (soic)
ps022517-0508 packaging z8 encore! xp ? f0822 series product specification 235 figure 63 displays the 28-pin pdip package available for z8 encore! xp f0822 series devices. figure 63. 28-pin plastic dual-inline package (pdip)
ps022517-0508 ordering information z8 encore! xp ? f0822 series product specification 236 ordering information order z8 encore! xp f0822 series from zilog ? , using the following part numbers . for more information regarding orde ring, consult your local zilog sales office. zilog website at www.zilog.com lists all regional offices and provides additional z8 encore! xp product information. part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description z8f08xx with 8 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f0821hh020sc 8 kb 1 kb 11 16 2 2 1 0 1 ssop 20-pin package z8f0821ph020sc 8 kb 1 kb 11 16 2 2 1 0 1 pdip 20-pin package z8f0822sj020sc 8 kb 1 kb 19 19 2 5 1 1 1 soic 28-pin package z8f0822pj020sc 8 kb 1 kb 19 19 2 5 1 1 1 pdip 28-pin package extended temperature: -40 to +105c z8f0821hh020ec 8 kb 1 kb 11 16 2 2 1 0 1 ssop 20-pin package z8f0821ph020ec 8 kb 1 kb 11 16 2 2 1 0 1 pdip 20-pin package z8f0822sj020ec 8 kb 1 kb 19 19 2 5 1 1 1 soic 28-pin package z8f0822pj020ec 8 kb 1 kb 19 19 2 5 1 1 1 pdip 28-pin package
ps022517-0508 ordering information z8 encore! xp ? f0822 series product specification 237 z8f08xx with 8 kb flash standard temperature: 0 c to 70 c z8f0811hh020sc 8 kb 1 kb 11 16 2 0 1 0 1 ssop 20-pin package z8f0811ph020sc 8 kb 1 kb 11 16 2 0 1 0 1 pdip 20-pin package z8f0812sj020sc 8 kb 1 kb 19 19 2 0 1 1 1 soic 28-pin package z8f0812pj020sc 8 kb 1 kb 19 19 2 0 1 1 1 pdip 28-pin package extended temperature: -40 c to +105 c z8f0811hh020ec 8 kb 1 kb 11 16 2 0 1 0 1 ssop 20-pin package z8f0811ph020ec 8 kb 1 kb 11 16 2 0 1 0 1 pdip 20-pin package z8f0812sj020ec 8 kb 1 kb 19 19 2 0 1 1 1 soic 28-pin package Z8F0812PJ020EC 8 kb 1 kb 19 19 2 0 1 1 1 pdip 28-pin package part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps022517-0508 ordering information z8 encore! xp ? f0822 series product specification 238 z8f04xx with 4 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f0421hh020sc 4 kb 1 kb 11 16 2 2 1 0 1 ssop 20-pin package z8f0421ph020sc 4 kb 1 kb 11 16 2 2 1 0 1 pdip 20-pin package z8f0422sj020sc 4 kb 1 kb 19 19 2 5 1 1 1 soic 28-pin package z8f0422pj020sc 4 kb 1 kb 19 19 2 5 1 1 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0421hh020ec 4 kb 1 kb 11 16 2 2 1 0 1 ssop 20-pin package z8f0421ph020ec 4 kb 1 kb 11 16 2 2 1 0 1 pdip 20-pin package z8f0422sj020ec 4 kb 1 kb 19 19 2 5 1 1 1 soic 28-pin package z8f0422pj020ec 4 kb 1 kb 19 19 2 5 1 1 1 pdip 28-pin package part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps022517-0508 ordering information z8 encore! xp ? f0822 series product specification 239 z8f04xx with 4 kb flash standard temperature: 0 c to 70 c z8f0411hh020sc 4 kb 1 kb 11 16 2 0 1 0 1 ssop 20-pin package z8f0411ph020sc 4 kb 1 kb 11 16 2 0 1 0 1 pdip 20-pin package z8f0412sj020sc 4 kb 1 kb 19 19 2 0 1 1 1 soic 28-pin package z8f0412pj020sc 4 kb 1 kb 19 19 2 0 1 1 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0411hh020ec 4 kb 1 kb 11 16 2 0 1 0 1 ssop 20-pin package z8f0411ph020ec 4 kb 1 kb 11 16 2 0 1 0 1 pdip 20-pin package z8f0412sj020ec 4 kb 1 kb 19 19 2 0 1 1 1 soic 28-pin package z8f0412pj020ec 4 kb 1 kb 19 19 2 0 1 1 1 pdip 28-pin package z8f08200100kitg development kit (20- and 28-pin) zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg opto-isolated usb smart cable accessory kit note: replace c with g for lead-free packaging. part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels i 2 c spi uarts with irda description
ps022517-0508 ordering information z8 encore! xp ? f0822 series product specification 240 part number suffix designations for example, part number z8f0821hh020sc is a z8 encore! xp flash 8 kb microcon- troller in a 20-pin ssop packag e, operating with a maximum 20 mhz external clock fre- quency over a 0 oc to +70 oc temperatur e range and built using the plastic-standard environmental flow. z8 f 08 21 h h 020 s c environmental flow c = plastic standard g = lead-free package temperature range (c) s = standard, 0 to 70 e = extended, ?40 to +105 speed 020 = 20 mhz pin count h = 20 j = 28 package h = ssop p = pdip s = soic device type 22 = 19 i/o lines, 5 adc channels, one spi 21 = 11 i/o lines, 2 adc channels, no spi 12 = 19 i/o lines, no adc channels, one spi 11 = 11 i/o lines, no adc channels, no spi memory size 08 = 8 kb flash, 1 kb ram 04 = 4 kb flash, 1 kb ram memory type f = flash device family z8 = zilog?s 8-bit microcontroller
ps022517-0508 index z8 encore! xp ? f0822 series product specification 241 index symbols # 212 % 212 @ 212 numerics 10-bit adc 4 40-lead plastic dual-inline package 234 a absolute maximum ratings 185 ac characteristics 194 adc 214 architecture 147 automatic power-down 148 block diagram 147 continuous conversion 148 control register 150 control register definitions 150 data high byte register 151 data low bits register 151 electrical characteristics and timing 199 operation 148 single-shot conversion 148 adcctl register 150 adcdh register 151 adcdl register 151 adcx 214 add 214 additional symbols 212 address space 13 addx 214 analog signals 10 analog-to-digital converter (adc) 147 and 217 andx 217 arithmetic instructions 214 assembly language programming 209 assembly language syntax 210 b b 212 b 211 baud rate generator, uart 99 bclr 215 binary number suffix 212 bit 215 bit 211 clear 215 manipulation instructions 215 set 215 set or clear 215 swap 215 , 218 test and jump 217 test and jump if non-zero 217 test and jump if zero 217 block diagram 3 block transfer instructions 215 brk 217 bset 215 bswap 215 , 218 btj 217 btjnz 217 btjz 217 c call procedure 217 capture mode 81 capture/compare mode 82 cc 211 ccf 216 characteristics, electrical 185 clear 216 clock phase (spi) 116 clr 216 com 217
ps022517-0508 index z8 encore! xp ? f0822 series product specification 242 compare 82 compare - extended addressing 214 compare mode 82 compare with carry 214 compare with carry - extended addressing 214 complement 217 complement carry flag 215 , 216 condition code 211 continuous conversion (adc) 148 continuous mode 81 control register definition, uart 100 control register, i2c 141 counter modes 81 cp 214 cpc 214 cpcx 214 cpu and peripheral overview 3 cpu control instructions 216 cpx 214 customer feedback form 251 customer feedback form 240 customer information 251 d da 211 , 214 data register, i2c 139 dc characteristics 187 debugger, on-chip 171 dec 214 decimal adjust 214 decrement 214 and jump non-zero 217 word 214 decw 214 destination operand 212 device, port availability 47 di 216 direct address 211 disable interrupts 216 djnz 217 dma controller 5 dst 212 e ei 216 electrical characteristics 185 adc 199 flash memory and timing 196 gpio input data sample timing 200 watch-dog timer 197 enable interrupt 216 er 211 extended addressing register 211 external pin reset 43 external rc oscillator 196 ez8 features 3 ez8 cpu features 3 ez8 cpu instruction classes 214 ez8 cpu instruction notation 210 ez8 cpu instruction set 209 ez8 cpu instruction summary 218 f fctl register 159 features, z8 encore! 1 first opcode map 231 flags 212 flags register 212 flash controller 4 option bit address space 163 option bit configuration - reset 163 program memory address 0001h 165 flash memory arrangement 154 byte programming 157 code protection 156 control register definitions 159 controller bypass 158 electrical characteristics and timing 196 flash control register 159 flash status register 160 frequency high and low byte registers 161 mass erase 158 operation 155
ps022517-0508 index z8 encore! xp ? f0822 series product specification 243 operation timing 155 page erase 158 page select register 160 fps register 160 fstat register 160 g gated mode 82 general-purpose i/o 47 gpio 4 , 47 alternate functions 47 architecture 47 control register definitions 49 input data sample timing 200 interrupts 49 port a-c pull-up enable sub-registers 54 port a-h address registers 50 port a-h alternate fu nction sub-registers 51 port a-h control registers 51 port a-h data direction sub-registers 51 port a-h high drive enable sub-registers 53 port a-h input data registers 54 port a-h output control sub-registers 52 port a-h output data registers 55 port a-h stop mode re covery sub-registers 53 port availability by device 47 port input timing 200 port output timing 201 h h 212 halt 216 halt mode 45 , 216 hexadecimal number prefix/suffix 212 i i2c 4 10-bit address read transaction 137 10-bit address transaction 134 10-bit addressed slave data transfer format 134 10-bit receive data format 137 7-bit address transaction 132 7-bit address, reading a transaction 136 7-bit addressed slave data transfer format 131 , 132 , 133 7-bit receive data transfer format 136 baud high and low byte registers 143 , 145 c status register 140 control register definitions 139 controller 127 controller signals 9 interrupts 128 operation 128 sda and scl signals 128 stop and start conditions 130 i2cbrh register 143 , 144 , 145 i2cbrl register 143 i2cctl register 141 i2cdata register 139 i2cstat register 140 im 211 immediate data 211 immediate operand prefix 212 inc 214 increment 214 increment word 214 incw 214 indexed 211 indirect address prefix 212 indirect register 211 indirect register pair 211 indirect working register 211 indirect working register pair 211 infrared encoder/decoder (irda) 109 instruction set, ez8 cpu 209 instructions adc 214 adcx 214 add 214 addx 214 and 217 andx 217 arithmetic 214 bclr 215 bit 215
ps022517-0508 index z8 encore! xp ? f0822 series product specification 244 bit manipulation 215 block transfer 215 brk 217 bset 215 bswap 215 , 218 btj 217 btjnz 217 btjz 217 call 217 ccf 215 , 216 clr 216 com 217 cp 214 cpc 214 cpcx 214 cpu control 216 cpx 214 da 214 dec 214 decw 214 di 216 djnz 217 ei 216 halt 216 inc 214 incw 214 iret 217 jp 217 ld 216 ldc 216 ldci 215 , 216 lde 216 ldei 215 ldx 216 lea 216 load 216 logical 217 mult 214 nop 216 or 217 orx 217 pop 216 popx 216 program control 217 push 216 pushx 216 rcf 215 , 216 ret 217 rl 218 rlc 218 rotate and shift 218 rr 218 rrc 218 sbc 215 scf 215 , 216 sra 218 srl 218 srp 216 stop 216 sub 215 subx 215 swap 218 tcm 215 tcmx 215 tm 215 tmx 215 trap 217 watch-dog timer refresh 216 xor 217 xorx 217 instructions, ez8 classes of 214 interrupt control register 67 interrupt controller 5 , 57 architecture 57 interrupt assertion types 60 interrupt vectors and priority 60 operation 59 register definitions 61 software interrupt assertion 60 interrupt edge select register 67 interrupt request 0 register 61 interrupt request 1 register 62 interrupt request 2 register 63 interrupt return 217 interrupt vector listing 57 interrupts not acknowledge 128 receive 128
ps022517-0508 index z8 encore! xp ? f0822 series product specification 245 spi 119 transmit 128 uart 97 introduction 1 ir 211 ir 211 irda architecture 109 block diagram 109 control register definitions 112 operation 109 receiving data 111 transmitting data 110 iret 217 irq0 enable high and low bit registers 63 irq1 enable high and low bit registers 64 irq2 enable high and low bit registers 65 irr 211 irr 211 j jp 217 jump, conditional, relative, and relative conditional 217 l ld 216 ldc 216 ldci 215 , 216 lde 216 ldei 215 , 216 ldx 216 lea 216 load 216 load constant 215 load constant to/ from program memory 216 load constant with auto-increment addresses 216 load effective address 216 load external data 216 load external data to/fro m data memory and auto- increment addresses 215 load external to/from data memory and auto-incre- ment addresses 216 load instructions 216 load using extended addressing 216 logical and 217 logical and/extended addressing 217 logical exclusive or 217 logical exclusive or/extended addressing 217 logical instructions 217 logical or 217 logical or/extended addressing 217 low power modes 45 m master interrupt enable 59 master-in, slave-out and-in 115 memory program 13 miso 115 mode capture 81 capture/compare 82 continuous 81 counter 81 gated 82 one-shot 81 pwm 81 modes 82 mosi 115 mult 214 multiply 214 multiprocessor mode, uart 95 n nop (no operation) 216 not acknowledge interrupt 128 notation b 211 cc 211 da 211 er 211 im 211 ir 211
ps022517-0508 index z8 encore! xp ? f0822 series product specification 246 ir 211 irr 211 irr 211 p 211 r 211 r 211 ra 211 rr 211 rr 211 vector 211 x 211 notational shorthand 211 o ocd architecture 171 auto-baud detector/generator 174 baud rate limits 174 block diagram 171 breakpoints 175 commands 176 control register 181 data format 173 dbg pin to rs-232 interface 172 debug mode 173 debugger break 217 interface 171 serial errors 174 status register 183 timing 202 ocd commands execute instruction (12h) 181 read data memory (0dh) 180 read ocd control register (05h) 179 read ocd revision (00h) 178 read ocd status register (02h) 178 read program counter (07h) 179 read program memory (0bh) 180 read program memory crc (0eh) 181 read register (09h) 179 read runtime counter (03h) 178 step instruction (10h) 181 stuff instruction (11h) 181 write data memory (0ch) 180 write ocd control register (04h) 178 write program counter (06h) 179 write program memory (0ah) 180 write register (08h) 179 on-chip debugger 5 on-chip debugger (ocd) 171 on-chip debugger signals 11 on-chip oscillator 167 one-shot mode 81 opcode map abbreviations 230 cell description 229 first 231 second after 1fh 232 operational description 89 or 217 ordering information 236 orx 217 oscillator signals 11 p p 211 packaging pdip 234 part selection guide 2 pc 212 pdip 234 peripheral ac and dc electrical characteristics 195 phase=0 timing (spi) 117 phase=1 timing (spi) 118 pin characteristics 12 polarity 211 pop 216 pop using extended addressing 216 popx 216 port availability, device 47 port input timing (gpio) 200 port output timing, gpio 201 power supply signals 11 power-down, automatic (adc) 148 power-on and voltage brown-out 195 power-on reset (por) 41
ps022517-0508 index z8 encore! xp ? f0822 series product specification 247 program control instructions 217 program counter 212 program flash configurations 153 program memory 13 , 153 push 216 push using extended addressing 216 pushx 216 pwm mode 81 pxaddr register 50 pxctl register 51 r r 211 r 211 rcf 215 , 216 receive 10-bit data format (i2c) 137 7-bit data transfer format (i2c) 136 irda data 111 receive interrupt 128 receiving uart data-interrupt-driven method 94 receiving uart data-polled method 93 register 124 , 211 adc control (adcctl) 150 adc data high byte (adcdh) 151 adc data low bits (adcdl) 151 baud low and high byte (i2c) 143 , 145 baud rate high and low byte (spi) 125 control (spi) 122 control, i2c 141 data, spi 121 flash control (fctl) 159 flash high and low byte (ffreqh and fre- eql) 161 flash page select (fps) 160 flash status (fstat) 160 gpio port a-h address (pxaddr) 50 gpio port a-h alternate function sub-registers 52 gpio port a-h control address (pxctl) 51 gpio port a-h data direction sub-registers 51 i2c baud rate high (i2cbrh) 143 , 144 , 145 i2c control (i2cctl) 141 i2c data (i2cdata) 139 i2c status 140 i2c status (i2cstat) 140 i2cbaud rate low (i2cbrl) 143 mode, spi 124 ocd control 181 ocd status 183 spi baud rate high byte (spibrh) 125 spi baud rate low byte (spibrl) 126 spi control (spictl) 122 spi data (spidata) 121 spi status (spistat) 123 status, i2c 140 status, spi 123 uartx baud rate high byte (uxbrh) 106 uartx baud rate low byte (uxbrl) 106 uartx control 0 (uxctl0) 103 , 106 uartx control 1 (uxctl1) 104 uartx receive data (uxrxd) 101 uartx status 0 (uxstat0) 101 uartx status 1 (uxstat1) 102 uartx transmit data (uxtxd) 100 watch-dog timer control (wdtctl) 86 watch-dog timer reload high byte (wdth) 88 watch-dog timer reload low byte (wdtl) 88 watch-dog timer reload upper byte (wdtu) 87 register address (ra) 211 register file 13 register file address map 15 register pair 211 register pointer 212 reset and stop mode characteristics 39 and stop mode recovery 39 carry flag 215 controller 5 sources 40 ret 217 return 217 rl 218 rlc 218 rotate and shift instructions 218 rotate left 218
ps022517-0508 index z8 encore! xp ? f0822 series product specification 248 rotate left through carry 218 rotate right 218 rotate right through carry 218 rp 212 rr 211 , 218 rr 211 rrc 218 s sbc 215 scf 215 , 216 sck 115 sda and scl (irda) signals 128 second opcode map after 1fh 232 serial clock 115 serial peripheral interface (spi) 113 set carry flag 215 , 216 set register pointer 216 shift right arithmetic 218 shift right logical 218 signal descriptions 9 single-shot conversion (adc) 148 sio 5 slave data transfer formats (i2c) 134 slave select 116 software trap 217 source operand 212 sp 212 spi architecture 113 baud rate generator 120 baud rate high and low byte register 125 clock phase 116 configured as slave 114 control register 122 control register definitions 121 data register 121 error detection 119 interrupts 119 mode fault error 119 mode register 124 multi-master operation 118 operation 114 overrun error 119 signals 115 single master, multiple slave system 114 single master, single slave system 113 status register 123 timing, phase = 0 117 timing, phase=1 118 spi controller signals 10 spi mode (spimode) 124 spibrh register 125 spibrl register 126 spictl register 122 spidata register 121 spimode register 124 spistat register 123 sra 218 src 212 srl 218 srp 216 ss, spi signal 115 stack pointer 212 status register, i2c 140 stop 216 stop mode 45 , 216 stop mode recovery sources 43 using a gpio port pin transition 44 using watch-dog timer time-out 44 sub 215 subtract 215 subtract - extended addressing 215 subtract with carry 215 subtract with carry - extended addressing 215 subx 215 swap 218 swap nibbles 218 symbols, additional 212 system and core resets 40 t tcm 215 tcmx 215 test complement under mask 215
ps022517-0508 index z8 encore! xp ? f0822 series product specification 249 test complement under mask - extended addressing 215 test under mask 215 test under mask - extended addressing 215 timer signals 10 timers 5 , 69 architecture 69 block diagram 70 capture mode 74 , 81 capture/compare mode 77 , 82 compare mode 75 , 82 continuous mode 71 , 81 counter mode 72 counter modes 81 gated mode 76 , 82 one-shot mode 70 , 81 operating mode 70 pwm mode 73 , 81 reading the timer count values 77 reload high and low byte registers 79 timer control register definitions 78 timer output signal operation 78 timers 0-3 control 0 registers 80 control registers 81 high and low byte registers 78 , 79 tm 215 tmx 215 transmit irda data 110 transmit interrupt 128 transmitting uart data-int errupt-driven method 92 transmitting uart data-polled method 91 trap 217 u uart 4 architecture 89 baud rate generator 99 baud rates table 107 control register definitions 100 controller signals 10 data format 90 interrupts 97 multiprocessor mode 95 receiving data using interrupt-driven method 94 receiving data using the polled method 93 transmitting data using the interrupt-driven method 92 transmitting data using the polled method 91 x baud rate high and low registers 106 x control 0 and control 1 registers 103 x status 0 and status 1 registers 101 , 102 uxbrh register 106 uxbrl register 106 uxctl0 register 103 , 106 uxctl1 register 104 uxrxd register 101 uxstat0 register 101 uxstat1 register 102 uxtxd register 100 v vector 211 voltage brown-out reset (vbr) 41 w watch-dog timer approximate time-out delay 83 cntl 42 control register 86 electrical characteristics and timing 197 interrupt in normal operation 84 refresh 84 , 216 reload unlock sequence 85 reload upper, high and low registers 87 reset 42 reset in normal operation 85 reset in stop mode 84 , 85 time-out response 84 wdtctl register 86 wdth register 88 wdtl register 88 working register 211
ps022517-0508 index z8 encore! xp ? f0822 series product specification 250 working register pair 211 wtdu register 87 x x 211 xor 217 xorx 217 z z8 encore! block diagram 3 features 1 introduction 1 part selection guide 2
ps022517-0508 customer support z8 encore! xp ? f0822 series product specification 251 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, pl ease visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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